FPGA Build System Engineer - Engineering Productivity - Sydney

Arista Networks
Sydney, NSWPosted 9 March 2026

Job Description

Who You'll Work With Arista Networks is looking for a skilled FPGA Build System Engineer for our Engineering Productivity (EngProd) team to design, optimize, and maintain build systems and CI/CD pipelines for FPGA development workflows.  As a part of the Engineering Productivity team, you will work with FPGA engineers and other team members to design, build, and administer secure, scalable, and fault-tolerant build infrastructure. Working in the EngProd group, you will collaborate with FPGA and software engineers to design, build, scale, and operate the build systems used by Arista's product development teams. You'll work with industry-standard tools including Jenkins, Ansible, Gerrit, Git, Docker, Kubernetes, and FPGA-specific toolchains. You'll automate build processes, optimize compilation times, and ensure our FPGA development workflows are efficient and reliable.   What You'll Do Design, implement, and optimize build systems for FPGA development workflows with focus on scalability, reliability, and performance Develop and maintain end-to-end CI/CD pipelines for FPGA projects using Jenkins Automate build processes using Python, Shell scripting, and Makefiles Build and deploy containerized build environments using Docker and manage orchestration with Kubernetes Monitor build system performance, identify bottlenecks, and implement optimization strategies to reduce build times Troubleshoot and debug complex build failures, dependency issues, and toolchain problems Implement infrastructure-as-code using Ansible for build system provisioning and configuration management Manage source control workflows and best practices using Git and Gerrit Work closely with FPGA engineers to understand requirements and improve developer experience Create and maintain build system documentation, runbooks, and architectural diagrams Proactively monitor build infrastructure, respond to alerts, and implement automated alert handling Plan and communicate maintenance windows for build infrastructure Survey and adopt best practices around build systems and CI/CD to maintain secure, scalable, and fault-tolerant infrastructure Write postmortem documents for build system incidents and implement solutions to prevent recurrence Essential Skills At least BSc Computer Science, Electrical Engineering, Computer Engineering + 3 years' experience, MS Computer Science or Engineering + 3 years' experience, or equivalent work experience Strong proficiency in Python and Shell/Bash scripting to implement complex automation workflows Experience writing and maintaining Makefiles for build automation Knowledge of Linux (or UNIX) from administration and debugging perspective with strong troubleshooting skills Proven hands-on experience designing and implementing build systems and end-to-end   CI/CD pipelines Experience with CI/CD tools such as Jenkins (preferred) or Bamboo Strong knowledge of Git for version control Essential: Solid experience with Docker and containerized build environments Strong understanding of Kubernetes concepts and container orchestration Experience with infrastructure-as-code frameworks like Ansible Strong problem-solving skills and ability to design scalable build system architectures Excellent communication and collaboration skills   Desired Skills TCL scripting knowledge Experience with FPGA design and build tools such as: Xilinx Vivado Xilinx ISE Intel Quartus ModelSim or other simulation tools Understanding of FPGA development workflows, synthesis, place-and-route, and timing closure Experience with Gerrit code review system (significant plus) Experience with Bitbucket  Experience managing version control systems like Perforce Knowledge of build optimization techniques and parallel build strategies Experience with monitoring and observability tools - Prometheus, Grafana, etc. Experience with infrastructure provisioning from storage and networking perspective Experienc ... (truncated, view full listing at source)