Senior Engineer, SoC Architect - Memory Subsystem

Lab Overview: The Samsung Research America SOC Architecture Lab provides innovative SoC architecture, bus / memory subsystem, multimedia subsystems and key IP blocks for future Samsung Galaxy products (Smartphones, tablets and future devices). We are defining the high performance SoC architecture development for various Galaxy device lineups. This lab collaborates with Samsung’s strategic SoC partners, Samsung MX headquarter team, and key RD teams around the globe to innovate and reinvent technology that will positively impact millions of people around the world via the Galaxy flagship products. Position Summary: We are looking for a SOC Architect Fabric, System Cache and DRAM Controller to help architect next generation SOCs. This is a highly visible hands-on role leading individual and team contributions to Fabric, System cache and DRAM controller sub-system architecture, interface, performance and power tradeoffs. Position Responsibilities: Guide on development of innovative Fabric, System cache, and DRAM controller Architectural and microarchitectural features to boost power and performance on various targeted workloads in next generation SOCs Identify and deliver Fabric, System cache, and DRAM controller subsystem architecture proposals for products in new and existing markets Evaluate architecture proposal benefits in collaboration with the team of SoC Architects and communicate the results across related engineering audiences (SW, HW, Architecture, Leadership) Perform high-level performance modeling/simulation and analysis of Fabric, System cache, and DRAM controller features, applications, benchmarks, and complex use cases Direct and orchestrate performance modeling, and studies to support inclusion of these features in the next generation “Fabric, System cache and DRAM controller” microarchitecture based on performance, area or power improvement Deliver architecture/microarchitecture proposals and specifications to the design team and articulate them effectively across audiences ranging from hardware software engineers to architecture community peers, and to technology leadership Collaborate with silicon bring-up and product teams to verify and debug the proposal and its delivered performance Collaborate across teams to bring microarchitectural proposals to fruition across the SOC, Driver, OS, and System through detailed documentation Required Skills: BSc, Master's, or PhD in Computer Science/Engineering, or equivalent combination of education, training, and experience 3+ years of experience in SOC or ASIC design and architecture Prior direct academic and/or work experience in Fabric/NoC, System Cache, DRAM controller Architect or microarchitecture is a plus Understanding of memory controller architecture, memory scheduling, prioritization and QoS Detailed knowledge of ARM bus infrastructure (ACE/AXI/AHB Fluid knowledge of one or more JEDEC standards, such as LPDDR, DDR, or HBM, and the ability to analyze such standards and drive recommendations Background in memory systems and computer architecture to understand the tradeoffs among memory bandwidth, latency, performance, power, and SoC area Special Attributes: Experience with BookSim Simulator Experience with Platform Architect Our total rewards programs are designed to motivate and engage exceptional talent. The base pay range for roles at this level is listed below, but may be higher or lower in other states due to geographic differentials in the labor market. Within the base pay range, individual rates depend on a number of factors—including the role’s function and location as well as the individual’s knowledge, skills, experience, education and training. This is part of our comprehensive compensation package with annual bonus eligibility and generous benefits to help you live life well. Base Pay Range $158,800 $218,100 USD Additional Information Disclosure of Trade Secrets Samsung has a strict policy on trade secrets. In applying to ... (truncated, view full listing at source)