SoC CPU Architect

Samsung Research America
665 Clyde Avenue, Mountain View, CA, USAPosted 12 March 2026

Job Description

Lab Summary: The Samsung Research America SOC Architecture Lab provides innovative SoC architecture, bus / memory subsystem, multimedia subsystems and key IP blocks for future Samsung Galaxy products (Smartphones, tablets and future devices). We are defining the high performance SoC architecture development for various Galaxy device lineups. This lab collaborates with Samsung’s strategic SoC partners, Samsung MX headquarter team, and key RD teams around the globe to innovate and reinvent technology that will positively impact millions of people around the world via the Galaxy flagship products. Position Summary: The CPU Architect role at Samsung Research America focuses on advancing technology solutions for smartphone and mobile platforms. In this role, you will be responsible for leading the development of high impact product. Role involves architecting, designing and modeling cutting edge CPU and its subsystem. This role requires both technical expertise and strong leadership skills to guide cross-functional team and ensure alignment with organization’s strategic goals. This role is integral to the SoC Architecture Lab, which is part of Samsung Research America and the extension of Samsung’s Mobile Experience Division. Position Responsibilities: Perform CPU microarchitecture modeling and simulations to evaluate performance, power, area and ensure design robustness Lead and participate in the design of key CPU components, including instruction pipelines, branch prediction, execution units, and memory subsystems Identify, debug, and resolve architectural and microarchitectural bottlenecks Drive continuous improvement initiatives by evaluating new tools, methodologies, and technologies for potential integration into the microarchitecture design flow Contribute to the CPU roadmap by identifying new techniques, features, and optimizations to stay ahead of industry trends Collaborate closely with SOC team to align CPU microarchitecture requirements with broader organizational objectives Required Skills: Bachelors, Msters or PhD in Electrical/Computer Engineering, Computer Science, related Science or equivalent combination of education, training and experience 15+ years of industry experience working experience in CPU architecture development Experience in CPU design and microarchitecture, with hands-on experience in developing and optimizing microarchitectures for high-performance CPU cores Strong understanding of CPU architectures, instruction sets (such as x86, ARM, RISC-V), and microarchitecture design principles (out-of-order execution, multi-level caches, branch prediction, etc.) Proven experience in microarchitecture modeling, simulation, and performance evaluation Deep knowledge of pipelining, superscalar execution, and out-of-order execution architectures Familiarity with memory hierarchies, including caches, TLBs, and memory management, cache coherence protocols etc Proficiency in architecture analysis and performance modeling, ranging from simple analytical models to complex cycle accurate performance model and correlation Strong modelling and simulator development skills and able to code in C, C++, python and similar programming languages Experience with power and performance trade-offs Our total rewards programs are designed to motivate and engage exceptional talent. The base pay range for roles at this level is listed below, but may be higher or lower in other states due to geographic differentials in the labor market. Within the base pay range, individual rates depend on a number of factors—including the role’s function and location as well as the individual’s knowledge, skills, experience, education and training. This is part of our comprehensive compensation package with annual bonus eligibility and generous benefits to help you live life well. Base Pay Range $188,400 $282,450 USD Additional Information Disclosure of Trade Secrets Samsung has a strict policy on trade secrets. In applying ... (truncated, view full listing at source)