Staff/Lead FPGA Engineer

Freeform Future Corp
Los Angeles, CA (On-site)$150k – $400kPosted 12 March 2026

Job Description

STAFF/LEAD FPGA ENGINEER Freeform builds AI-native manufacturing systems that unify software, hardware, and physics to produce industrial-scale parts at the speed of human ideation. By treating manufacturing as a single integrated system, we unlock a new era of innovation where complex hardware is designed, built, and scaled without limits. As a Staff/Lead FPGA Engineer at Freeform, you will be responsible for architecting and implementing a custom compute platform that enables the world’s first AI-driven, intelligent metal 3D printing technology. You will use the latest and greatest in FPGA’s including the Xilinx Zynq Ultrascale+ MPSoC to scale a high-throughput, low latency image processing pipeline. You will also have an opportunity to integrate your FPGA solutions with state-of-the-art GPUs to create an advanced machine learning acceleration platform. You will drive interdisciplinary engineering efforts between software, electrical, and process engineering teams to rapidly innovate custom FPGA solutions. High-performance computing to central to what makes Freeform’s technology unique and powerful, so this is a high-impact role in which you’ll develop core IP for a world-changing technology. 3D printing experience is not required to be successful here - rather we look for smart, motivated, collaborative engineers who love solving hard problems and creating amazing technology! Responsibilities: Architect and implement FPGA solutions to scale a high-throughput, ultra-low latency image processing pipeline Lead interdisciplinary efforts between software, electrical, and process engineering to drive innovation on FPGA capabilities Architect and implement custom FPGA capabilities to enable real-time machine learning Architect and implement new logic components for use on FPGAs Implement custom algorithms on FPGAs for signal processing Implement custom controllers on FPGAs Basic Qualifications: Bachelor’s degree in computer engineering, electrical engineering, computer science, or related field 10+ years of FPGA development experience in SystemVerilog or VHDL Familiarity with Xilinx Vivado/Vitis toolchain development environment Experience with high-speed IO, board bring up, and similar hardware-centric FPGA development domains Nice to Have: Master’s degree in computer engineering, electrical engineering, computer science, or related field Experience with image processing or DSP Experience with Xilinx Zynq Ultrascale+ MPSoC Experience with embedded software development including embedded Linux and System on Chip (SoC)-based architectures Experience implementing math/advanced computations on FPGAs Experience with heterogeneous computing platforms and high-speed data acquisition systems Familiarity with C/C++ or other high-level programming languages Excellent verbal and written communication skills Creative thinker able to apply first-principles reasoning to solve complex problems Location: Based in Hawthorne, our vertically integrated facility brings technology development, RD, and production together under one roof. We operate at the center of LA’s deep tech ecosystem, surrounded by some of the most ambitious hardware innovation happening anywhere in the country. What We Offer: We have an inclusive and diverse culture that values collaboration, learning, and making deliberate data-driven decisions. We offer a unique opportunity to be an early and integral member of a rapidly growing company that is scaling a world-changing technology. Benefits Significant stock option packages 100% employer-paid Medical, Dental, and Vision insurance (premium PPO and HMO options) Life insurance Traditional and Roth 401(k) Relocation assistance provided Paid vacation, sick leave, and company holidays Generous Paid Parental Leave and extended transition back to work for the birthing parent Free daily catered lunch and dinner, and fully stocked kitchenette Casual dress, flexible work hours, and regular catered ... (truncated, view full listing at source)