Senior Systems Performance Engineer
Crusoe CloudSan Francisco, CA - US$173k – $210kPosted 18 March 2026
Job Description
Senior Systems Performance Engineer
Crusoe is on a mission to accelerate the abundance of energy and intelligence. As the only vertically integrated AI infrastructure company built from the ground up, we own and operate each layer of the stack — from electrons to tokens — to power the world's most ambitious AI workloads. When you join Crusoe, you join a team that is building the future, faster.
We're in the midst of the greatest industrial revolution of our time. The demand for AI compute is boundless, and power is a bottleneck. We're solving that — with an energy-first approach that makes AI infrastructure better for the world and faster for the people innovating with AI.
We're looking for problem-solving, opportunity-finding teammates with a sense of urgency, who believe in the scale of our ambition and thrive on a path not fully paved — people who want to grow their careers alongside a team of experts across energy, manufacturing, data center construction, and cloud services.
If you want to do the most meaningful work of your career, help our customers and partners advance their AI strategies, and be part of a high-performing team that believes in each other, come build with us at Crusoe.
SENIOR SYSTEMS PERFORMANCE ENGINEER
SAN FRANCISCO, SUNNYVALE (ONSITE)
ROLE MISSION
At Crusoe, we are pioneering the future of sustainable computing. We are seeking a Senior Performance Engineer to serve as a technical lead for the end-to-end hardware evaluation, reliability, and scaling of our AI infrastructure. You will be responsible for defining the performance roadmap of our next-generation cloud, ensuring that our SOTA (State-of-the-Art) AI models run with peak efficiency across diverse hardware architectures.
WHAT YOU’LL BE WORKING ON:
- Architectural Strategy: Lead the evaluation and establishment of New Product Introduction (NPI) across varied hardware architectures, focusing on Bare Metal and VM environments.
- Full-Stack Optimization: Conduct deep-dive performance evaluations and workload characterizations across compute, memory, storage, and networking.
- Performance Modeling: Develop sophisticated multi-variable projection models and frameworks to analyze system design options through KPI tradeoffs, such as Power and TCO (Total Cost of Ownership).
- Hardware-Software Co-Design: Collaborate with external vendors to drive platform customization and optimize server/AI architectures for maximum performance-per-TCO.
- Infrastructure Scaling: Design and implement 0-to-1 performance methodologies that allow the team to scale evaluation processes for large-scale GPU/AI data centers.
- Industry Leadership: Actively engage in industry research and contribute technical insights to consortiums and standards committees to influence future hardware roadmaps.
WHAT YOU’LL BRING TO THE TEAM:
- 5+ Years experience in end-to-end hardware evaluation, reliability, and scaling of our AI infrastructure
- Large-Scale Systems: Proven experience in building and optimizing AI application systems for large-scale GPU infrastructure.
- Architecture & Microarchitecture: Deep knowledge of x86 and ARM architectures, including competitive analysis of microarchitecture and performance-based validation.
- Programming & Tooling: Expert-level proficiency in Python and C++. Experience with cycle-accurate simulators and hardware debuggers like Lauterbach Trace32 or ARM DS-5 is essential.
- Low-Level Systems: Ability to write and debug ARMv8 assembly, implement data synchronization protocols (MESI/MOESI), and analyze RTL via simulation waveforms.
- Security & HPC: Experience with performance modeling for secure environments (e.g., Intel SGX, TDX, VM Encryption) and high-performance computing benchmarks.
COMPENSATION:
Compensation will be paid in the range of $172,500 - $210,000. Restricted Stock Units are included in all offers. Compensation to be determined by the applicant’s education, experience, knowledge, skills, and abilities, as well as ... (truncated, view full listing at source)
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