Mid-level FPGA Engineer (AU)

DroneShield
Sydney, AustraliaPosted 24 March 2026

Job Description

Work with cutting edge AI technology, making the world a safer and more secure place. DroneShield (ASX:DRO) offers an opportunity to solve some of world’s most challenging technical problems in the rapidly growing counter-drone sector. Our customers operate in some of the most challenging and high-stakes environments in the world, including military organisations, government agencies, airports, critical infrastructure operators, and law enforcement. Protecting airspace in these settings requires technology that performs under pressure and teams that understand what’s at stake. At DroneShield, employees work at the leading edge of counter-drone innovation, helping to address real-world security challenges as drone threats continue to evolve globally. With one of the largest listed defence company market capitalisations in Australia, now part of the ASX200 index, DroneShield is experiencing a period of hypergrowth. Revenue has surged from A$57 million in 2024 to over A$217 million in 2025, representing growth of more than 400% year-on-year, with record profitability and cashflow. The total addressable global market for counter-drone is assessed at approximately $100 billion, and is currently at the nascent stage with much of the growth still to come, with DroneShield well positioned as a global market leader, and the only public listed pure-play business in this sector. The company has grown from 11 employees in 2017 to over 450 staff globally today, and is on track to reach around 550 by the end of 2026. This expansion includes investment of over A$50 million annually in R&D, a global pipeline exceeding A$2.5 billion, and continuous scaling of production capacity to meet accelerating demand. The role is based at DroneShield’s central Sydney headquarters. Overseas on-the-ground presence includes Virginia (USA), Netherlands, Denmark, Mexico and Dubai, as well as distributors in over 70 countries worldwide. About the role DroneShield is seeking a Mid-level FPGA Engineer to join our team in Sydney, Australia, reporting to the Team Lead, FPGA. This role focuses on developing and scaling drone recognition and disruption capabilities using software-defined radios (SDRs). You will design and implement FPGA-based systems for real-time Digital Signal Processing, translating complex algorithms into production-grade firmware. The role also involves building robust verification frameworks, including cocotb simulations and hardware-in-the-loop testing, integrated into CI/CD pipelines. Responsibilities, Duties and Expectations Design, development, document and implementation of FPGA-based systems to support real-time Digital Signal Processing Architect and automate comprehensive test procedures - develop cocotb simulation models and hardware in the loop tests to be included in CI/CD pipeline integration Develop supporting C++ firmware for embedded systems, including control, configuration, and communication interfaces Qualifications, Experience and Skills BS/BE degree in Electronic Engineering, similar technical field of study or equivalent practical experience 2 to 5 years of experience working with FPGAs Strong experience with programming, debugging, and verifying Verilog, VHDL or SystemVerilog Experience writing modern C++ (C++14/17/20) for embedded firmware Experience with synthesis and timing closure on resource constrained FPGAs FPGA development experience using tools such as Vivado (preferable), Quartus, Vitis etc Experience with designing and implementing high-throughput, low-latency and fully pipelined FPGA architectures Nice to have: Experience working in a Linux environment Experience with RFSoC and software defined radios (SDR) is highly desirable Familiarity with scripting languages (Python Preferable) Experience working with PCB schematics, board bring-ups and debugging hardware is highly desirable Strong background and experience in Digital Signal Processing A general RF background and knowledge of RF ... (truncated, view full listing at source)
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