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🍪 Privacy Notice This website uses cookies to improve your web experience. By using the site, you agree to the use of cookies. dismiss Senior Analog/RFIC Design Engineer Saratoga, CAE-Space US – Engineering, Manufacturing & Operations /Full-Time /On-Site APPLY FOR THIS JOB Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place! E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems. We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life. We are seeking a highly skilled and experienced Senior Analog/RFIC Design Engineer to join our engineering team. In this role, you will be responsible for designing, simulating, and verifying high-performance analog and RF integrated circuits for applications such as 5G, IoT, and satellite communications. You will collaborate with cross-functional teams to define requirements, develop innovative design solutions, and ensure that products meet the highest standards of quality and performance. What you will be doing: Analog/RF Circuit Design: Design, simulate, and optimize analog and RF IC blocks such as amplifiers, mixers, oscillators, filters, phase-locked loops (PLLs), low-noise amplifiers (LNAs), and power amplifiers (PAs) Develop high-performance designs that meet stringent requirements for power, noise, and linearity Simulation and Verification: Conduct detailed circuit simulations and optimizations using industry-standard EDA tools (Cadence, Mentor Graphics, etc.) Perform pre-tapeout and post-layout verification to ensure design integrity and performance specifications are met Layout and Parasitic Extraction: Guide layout engineers on the physical implementation of analog/RF blocks, with an understanding of the impact of parasitics and layout dependencies Conduct post-layout simulations and resolve layout-related issues to meet performance and yield targets Test and Validation: Collaborate with test engineers to define test strategies and design-for-test (DFT) implementations Support silicon validation and debugging, providing technical expertise to ensure successful first-pass silicon Cross-functional Collaboration: Work with system architects, digital designers, and process technology teams to align on project specifications and timelines Support product and test engineering teams in production ramp and yield improvement activities Documentation and Reporting: Document design processes, circuit blocks, and simulation results in detail Present design reviews and progress updates to internal teams and management What you bring to this role: Minimum of 5-10 years of experience in analog and RFIC design, with a track record of successful product tape-outs Proficient in analog/RF circuit design for ICs in CMOS technology Strong expertise with Cadence Spectre, Mentor Graphics, or similar EDA tools Solid understanding of analog/RF principles, including matching, noise, stability, and non-linearity Excellent problem-solving skills, attention to detail, strong communication abilities, and an aptitude for working in a collaborative environment Bonus points for the following: MS or Ph.D. in Electrical Engineering or related field, with a focus on Analog/RFIC design Experience with high-frequency circuit design (GHz range) and high-speed data converters Knowledge of mixed-signal IC design, including ADC/DAC design and integration of analog and digital components Experience with RF system design for wireless communications (LTE, 5G, etc. Thi ... (truncated, view full listing at source)