Senior Engineering Manager, Network Observability
CrusoeSunnyvale, CA - US$237k – $288kPosted 27 March 2026
Job Description
Senior Engineering Manager, Network Observability
Crusoe is on a mission to accelerate the abundance of energy and intelligence. As the only vertically integrated AI infrastructure company built from the ground up, we own and operate each layer of the stack — from electrons to tokens — to power the world's most ambitious AI workloads. When you join Crusoe, you join a team that is building the future, faster.
We're in the midst of the greatest industrial revolution of our time. The demand for AI compute is boundless, and power is a bottleneck. We're solving that — with an energy-first approach that makes AI infrastructure better for the world and faster for the people innovating with AI.
We're looking for problem-solving, opportunity-finding teammates with a sense of urgency, who believe in the scale of our ambition and thrive on a path not fully paved — people who want to grow their careers alongside a team of experts across energy, manufacturing, data center construction, and cloud services.
If you want to do the most meaningful work of your career, help our customers and partners advance their AI strategies, and be part of a high-performing team that believes in each other, come build with us at Crusoe.
About this Role
Crusoe Cloud is seeking a visionary and technical leader to spearhead Network Development across our global infrastructure. While our Operations team ensures the reliability of our current fleet, the Network Development team is responsible for the design, engineering, and evolution of the high-performance fabrics that make Crusoe a leader in AI and HPC.
The ideal candidate is a "builder" at heart. You will lead the team responsible for translating complex architectural requirements into scalable, automated, and high-performance network designs. From optimizing GPU-to-GPU communication in our HPC clusters to developing the automation frameworks that deploy our global backbone, you will be at the forefront of networking for the AI era.
What You’ll Be Working On:
- Lead Network Engineering & Design: Own the end-to-end development lifecycle of Crusoe’s network architecture, focusing on the next generation of GPU fabrics and global interconnects.
- Innovate HPC & AI Fabrics: Drive the engineering of low-latency, high-bandwidth networks (RoCEv2, InfiniBand) specifically optimized for massive-scale distributed AI training.
- Define the Automation Roadmap: Architect and implement "Network-as-Code" initiatives. Lead the development of CI/CD pipelines for network configurations, automated provisioning, and self-healing infrastructure.
- Hardware Strategy & Vendor Engineering: Evaluate and certify next-generation hardware platforms. Partner with vendors (Arista, NVIDIA, Juniper) to influence product roadmaps and ensure Crusoe has the best-in-class silicon for our workloads.
- Build and Mentor a Development Culture: Recruit and lead a team of Network Development Engineers (NDE) and Software Engineers who bridge the gap between traditional networking and software engineering.
- Cross-Functional Product Partnership: Collaborate closely with Product, Hardware Engineering, and Network Operations to ensure new designs are not only high-performance but also observable and maintainable at scale.
What You’ll Bring to the Team:
- 15+ years of progressive experience in large-scale network engineering, with at least 5+ years in a leadership role focused on network design, architecture, or development.
- Deep expertise in Data Center Fabric Design: Proven track record building large-scale Clos topologies using BGP, EVPN-VXLAN, and Segment Routing.
- Specialized HPC Knowledge: Deep understanding of the "Backend Network," including RDMA, RoCEv2, and InfiniBand, and how they impact GPU performance.
- Software-Defined Mindset: Strong background in network programmability and automation frameworks (Python, Go, Terraform, Ansible, NetBox, or custom-built controllers).
- Hardware Proficiency: Experience with merchant sil ... (truncated, view full listing at source)
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