Senior Design Verification Engineer- Mixed Signal IP

Job Details: Job Description: The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful. Responsibilities: Performs functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to mixed signal microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with digital and analog architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences. Minimum Qualifications: The candidate must possess a BS degree in Computer Engineering/Computer Science/Electrical Engineering or related field with 8 years of relevant industry experience in Design verification, System Verilog and OVM/UVM or MS degree in Computer Engineering/Computer Science/Electrical Engineering or related field with 6 years of relevant industry experience or a PhD in Computer Engineering/Computer Science/Electrical Engineering or related field with & 4 years in the following: Design verification System Verilog OVM/UVM Preferred Qualifications: The candidate must be experienced in validation flow right from test plan creation to verification closure, waveform debug, functional coverage, code coverage, VCS NLP and non-NLP simulations and GLS. Knowledge of DDRPHY validation with good hold on DFI/DDR/LPDDR protocols. Experience in scripting skills in Python/Perl. Exposure to Formal Property Verification and Git/Perforce/CVS version control Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Folsom Additional Locations: US, California, Santa Clara Business group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, geneti ... (truncated, view full listing at source)