Senior Design Verification Engineer

Job Details: Job Description: Embark with us on a journey of growth and transformation as we create exceptionally engineered technology and bring AI everywhere. As a valued team member, your adaptability and attention to detail will contribute to our drive for results and relentless pursuit of quality, ensuring we meet our customers' needs with precision. Join us and build on our legacy of innovation and collaboration as we deliver world‑changing technology that improves the life of every person on the planet. Life at Intel: https://jobs.intel.com/en/life-at-intel Intel is seeking a Senior Design Verification Engineer for the Silicon Chassis team. In this role, you will own end-to-end verification of critical chassis and interconnect IP blocks from planning through signoff. You will drive quality in testbench architecture, test plan and coverage closure while working closely with architecture, design, and software teams. This position requires strong technical depth in DV methodologies, protocol verification, and memory subsystem behavior, with enough breadth in RTL, physical design, and CAD to contribute across traditional discipline boundaries. AI-assisted workflows are part of everyday development here. Consistent execution against schedule and quality goals is expected. Responsibilities include but are not limited to: Own verification planning and execution for key IP features across IP and subsystem integration points Build scalable verification environments and targeted testplans with reusable testbenches, checkers, VIPs, and behavioral models Collaborate closely with architecture, design, and software teams from specification through bringup; contribute across role boundaries when needed to unblock progress and maintain execution quality Drive ownership of multiple critical blocks and verification components; take full responsibility for functional signoffs and achievement of performance and power metrics Lead IP delivery to multiple customers while ensuring technical excellence; balance competing requirements, schedules, and resources across teams Drive convergence of simulation and formal verification into unified bug hunting and coverage closure strategies; evaluate and adopt emerging methodologies including ML-driven verification flows Mentor and develop verification engineers; establish verification best practices and raise team-level execution quality Qualifications: You must possess the minimum qualifications below to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Bachelor's Degree in Electrical Engineering, Computer Science, or related field, with 9 years of relevant experience OR Master's degree in Electrical Engineering, Computer Science, or related field, with 6 years of relevant experience in design verification; extensive background in IP DV with significant, demonstrated experience in subsystem and SoC-level verification Proven deep expertise in interconnects, caches, and memory subsystems, including multiple bus protocols such as AMBA (CHI, ACE, AXI), PCIe, UCIe, and CXL; cache coherency and memory consistency models- Demonstrated experience in verification of global functions including debug, trace, clock and power management, RAS, QoS, and security features Strong background in simulation and formal verification methodologies including UVM, SVA, ABV, and co-simulation; proficiency in low-power verification techniques, HDL/verification languages, and industry-standard EDA tools Advanced hands-on coding proficiency across SystemVerilog/UVM, C/C, Python, and build systems; comfort using AI-assisted development tools as part of everyday workflow; track record of delivering reusable, configurable verification collateral Working familiarity with RTL, physical design, and CAD tool flows; enough to read, review, and contribute outside core ... (truncated, view full listing at source)