Systems and Hardware Enabling Engineer
Intel2 Locations$122k – $232kPosted 27 March 2026
Job Description
Job Details:
Job Description:
Join a passionate team of engineers in Intel's Networking Solutions Group (NSG) focused on enabling next generation programmable Infrastructure Processing Units (IPUs) with our lead customers as part of the Customer Experience Support (CES) organization. Intel brings decades of leadership in networking, virtualization, packet processing, storage, and security to a new class of IPU products that accelerate host networking functions and support emerging use cases such as security, virtualization, storage, load balancing, and data path optimization.
Working closely with major cloud service providers and Intel development teams, you will help deliver customized IPU based solutions that enhance isolation, security, performance, and system management for our customers.
Projects and responsibilities include but are not limited to:
Provide technical support to customers for solutions that incorporate one or more Intel Ethernet products and technologies, helping customers to deliver quality design, accelerating overall design cycle and time to market readiness
Deliver board/platform bring up, validation, debug and issue resolution support for IPU hardware across development, testing, and production phases for both Intel and customer designs.
Evaluates and develops new tools/ software to debug/improve overall efficiency that optimize product quality and performance.
Develop application notes, user guides, white papers, and other technical collaterals to streamline customer adoption of Intel products.
Analyze customer designs and voice-of-customer data to provide actionable feedback to PAE, Engineering, and Planning teams for current and future products.
Partner with stakeholders across engineering, marketing, and program management to integrate customer requirements, support product ramps, deliver training, and ensure product health with rapid technical support and continuous improvement.
Qualifications:
Candidates must possess the following minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor.
Minimum Qualifications:
Bachelor's degree in Electrical or Computer Engineering or related field of study with 4 years of industry experience, or Master's degree in Electrical or Computer Engineering or related field of study with 2 years of industry experience.
2 years of experience in hardware design, board level debugging, bring up, and testing on Intel or ARM architectures.
2 years of experience with modern computer networking architectures, protocols, topologies, and networking products.
Experience working in a lab environment with lab tools such as oscilloscopes, and multimeters.
Experience with schematics and layout files.
Experience with programming and scripting (e.g., Python).
Preferred Qualifications:
Demonstrated experience enabling new products directly with customers.
Experience in system level server or network debugging across hardware, firmware, and software.
Knowledge of Ethernet products and ecosystem for Enterprise and Data center
Knowledge of operating systems, firmware, BIOS, device drivers, databases, system administration, network administration, application administration, and embedded software/firmware tools.
Understanding system and board-level design tradeoffs for high performance NIC integration (thermal, power, signal integrity, BMC, BIOS integration).
System admin or network admin-level experience with scaled datacenter workloads (e.g., databases, load balancers, web servers, switch configuration) is a plus.
Ability to work and communicate effectively with cross-functional teams across multiple time zones, with a strong customer-focused mindset.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, California, Santa Clara
Business group:
The Central Engineeri ... (truncated, view full listing at source)
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