Process Integration Engineer - Defect Metrology Layer Owner

Job Details: Job Description: Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Want to learn more? Visit our YouTube Channel or the link below. Life at Intel At Intel's Logic Technology Development (LTD) we have continued to extend Moore's law to be world leaders in computing technology. To achieve the necessary scaling of our semiconductor manufacturing process, we have led the industry in developing enhancements such as strained silicon for carrier transport enhancement, high-k metal gates, and FINFETs. LTD has been at the center of every new development that has kept Moore's Law moving forward. Defect Metrology plays a key role in the development of every new silicon process development. Our analysis builds the plan that allows LTD to take a technology from the research phase to the high-volume manufacturing phase while maintaining high quality standards. In MIE, we engineer world-class yields on D1 processes by driving defects down to Best in Class targets. As a Defect Metrology engineer, you will be responsible for identifying all the defects that impact yield and performance in an advanced silicon process technology. You will characterize the process using cutting-edge metrology tools. With this characterization, you will be responsible for creating the defect reduction roadmap. You will then work directly with modules and integration to drive that roadmap by developing and qualifying process fixes. This role provides an opportunity to influence Intel's future process technologies that will keep Moore's Law moving forward. Responsibilities/Duties include but not limited to: Provide navigation and leadership to meet Intel's yield objectives utilizing state of the art metrology tools and QTMs. Organizing and presenting defect summaries to LTD engineering teams. Partnering with Intel Integration, Yield, and failure analysis labs to provide root cause for all defect issues. Institute ramp to manufacturing volumes to demonstrate the technology meets requirements while simultaneously transferring the technology to counterparts in manufacturing via the Copy Exactly Methodology. Hold the team and collaborators accountable for quality through IMT and FTs. Work collaboratively as a part of the overall TD Defect metrology group. Role-model and establish a team culture of trust, collaboration, safety, accountability, and excellence. Build strong relationships with other LTD process and design teams based on mutual trust and respect. An ideal candidate should be willing to demonstrate the below behavioral traits: Strong data analysis and problem debug skills. Excellent communication skills. Willingness to confidently present complex material to decision makers at all levels of the organization. Understand and adhere to key Intel values Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences. Minimum Qualifications: • Bachelors degree and 6 years of experience OR a Master's degree with 4 years of experience in Computer Science, Physics, Material Science and Engineering, Chemical Engineering, Electrical Engineering, Mechanical Engineering, Nuclear engineering, Optics, Chemistry, or similar field of study., OR PhD in Computer Science, Physics, Material Science and Engineering, Chemical Engineering, ... (truncated, view full listing at source)