Senior Layout Design Engineer

Job Details: Job Description: This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of your resume will be required to be considered for this position. As a Senior Layout Design Engineer within the DTP AMS group, you will play a pivotal role in delivering best-in-class IO IPs on leading-edge process nodes. You will work at the intersection of circuit design, process technology, and automation to achieve aggressive Power, Performance, and Area (PPA) targets. This role requires a blend of artistic precision in manual layout and a strategic mindset to drive CAD automation and methodology improvements. Primary Responsibilities IP Architecture: Architect and implement complex analog and mixed-signal layouts for IO IPs, ensuring strict adherence to performance targets and design specifications. Global Technical Leadership: Act as a technical anchor across global sites (including India and Mexico), ensuring seamless project hand-offs and maintaining design consistency across time zones. Floorplanning and Integration: Develop sophisticated chip-level floorplans, robust power grids, and optimized ESD/bump structures. Electrical Integrity: Execute precise micro-floorplanning and detailed signal routing using advanced techniques (shielding, matching, and parasitic balancing) to mitigate layout-dependent effects. Comprehensive Verification: Own the full suite of verification tasks, including DRC, LVS, and antenna checks, as well as reliability assessments such as Electromigration (EM) and IR drop analysis. Additional Responsibilities Methodology and Automation: Identify bottlenecks in the design flow and develop new CAD-based automations or scripting solutions to enhance team productivity and layout quality. Cross-Functional Collaboration: Partner with Technology Development (TD), Circuit Design, and Packaging teams to negotiate layout tradeoffs and define IP requirements for next-generation nodes. Technical Troubleshooting: Act as a subject matter expert to resolve complex design gaps and tool-related issues, ensuring project milestones remain on track. Quality and Reliability (QnR): Collaborate with QnR engineers to interpret and implement advanced reliability requirements and process-specific design rules. Mentorship and Peer Review: Provide technical guidance to junior engineers and participate in layout reviews to ensure best-in-class standards are maintained across the team. Required Skills and Qualifications Expertise in Advanced Nodes: Deep understanding of layout challenges in FinFET and leading-edge process technologies. Tool Proficiency: Mastery of industry-standard EDA tools (e.g., Cadence Virtuoso, synopsys, Mentor Calibre). Analytical Mindset: Strong grasp of the physical effects impacting analog performance (e.g., LOD, WPE, Parasitic Extraction). Innovation-Driven: Proven ability to use scripting (SKILL, Python, or Perl) to automate repetitive tasks. Qualifications: Minimum qualifications are required to be initially considered for this position.  Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Component Engineer-ing, or in a related field 6 years of experience in one or more of the following areas: Device-level CMOS analog/memory custom layout design Hierarchical layout floor-planning and integration EDA tools (DRC/LVS verification, CMOS processes) Experience with basic integrated circuit operation fundamentals Unix/Linux environment expertise Advance English level. Must have unrestricted, permanent right to work in Mexico (this role is not eligible for vi-sa or immigration sponsorship). Preferred Qualifications: Post Graduate degree in Electrical Engineering, Computer Engineering, Component Engineering, or in a ... (truncated, view full listing at source)