Intel Foundry Advanced Device Development Engineer
Intel2 LocationsPosted 27 March 2026
Tech Stack
Job Description
Job Details:
Job Description:
This position is in the Logic Technology Development team working in one of the most advanced semiconductor cleanroom facilities in the world. You will be designing, executing, and analyzing experiments necessary to meet engineering specifications for their process.
What we offer
We foster a collaborative, supportive, and exciting environment where the brightest minds in the world come together to achieve exceptional results. We give you opportunities to transform technology and create a better future, by delivering products that make the world a better place. Intel Corporation Core Values here.
Benefits
We provide benefits that promote a healthy, enjoyable life: excellent medical plans, wellness programs, and amenities, time off, recreational activities, discounts on various products and services, and many more creative rewards that make Intel a Great Place to Work.
What we do
The Logic Technology Development (LTD) organization delivers the latest process technology innovations to drive Intel's amazing product roadmap. Look at Life Inside Intel here.
What you will be considered for
LTD Advanced Device Development Engineers are responsible for leading scientific research enabling the manufacture of innovative device architectures, including but not limited to:
Set advanced device performance targets for Process Design Kit releases and Interface with Design and Foundry partners to address circuit-level issues.
Assess Silicon-to-Simulation health and readiness for High Volume Manufacturing.
Define robust test structures and test programs to validate advanced design rules and reliably extract key device parameters.
Use Statistics, Data Mining, and other data analysis techniques to collect, explore, and extract insights from Electrical-test, yield, and fab data to define future development direction.
Qualifications:
Qualifications
You must possess the minimum qualifications below to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. The experience listed below would be obtained through a combination of your schoolwork/classes/ experimental research and/or relevant previous job and/or internship experiences.
Minimum Qualifications
Must possess a minimum of master's degree with 2-years' industry experiences or Ph.D. degree in electrical engineering (EE), electrical and computer engineering (ECE), electrical engineering and computer science (EECS) directly related to Semiconductor field.
Minimum of 6 months of experience in one or more of the following: 1) Semiconductor materials, fabrication, and device physics; 2) Electrical characterization of Semiconductor Devices (transistor, diode, etc.)
Preferred Qualifications
Advanced Transistor Device Structures and Device Physics.
Process monitoring Test structures design and layout experience.
Device and circuit simulation.
Statistical Process Control (SPC) or Design of Experiments (DOE) principles and engineering analysis tools.
Expertise in database structures, research methods, machine learning, analytics packages (i.e., JMP, MATLAB, Octave), scripting languages (i.e., Python, JSL, Perl, TCL), or programming languages (i.e., SQL, C/C)
Job Type:
Experienced Hire
Shift:
Shift 1 (Taiwan)
Primary Location:
Taiwan, Taipei
Additional Locations:
Taiwan, Hsinchu
Business group:
Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capa ... (truncated, view full listing at source)
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