Senior RFIC Layout Designer

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we’re mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space. The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today’s and tomorrow’s massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits. With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we’d love for you to apply. The Role We are seeking a Senior RFIC Layout Designer to drive the physical implementation of advanced RF and mixed-signal integrated circuits for next-generation satellite communication systems. This is a senior individual contributor role focused on hands-on layout execution and top-level integration, working closely with cross-functional teams to deliver high-performance silicon. Responsibilities Execute high-quality layout for RF, analog, and mixed-signal blocks in advanced FinFET nodes (e.g., LNA, RF amplifiers, mixers, PLL, LO generation, ADC/DAC, baseband filters, bandgap/bias/LDO) Contribute to top-level layout integration, including block placement, routing, power planning, and floorplanning. Contribute to layout strategies to meet performance, area, power, reliability, and manufacturability targets. Ensure robust implementation of matching and symmetry for sensitive RF/analog structures, and high-frequency routing and parasitic control. Ensure robust implementation of EM/IR, ESD, latch-up, and reliability considerations Collaborate closely with RF/analog designers, digital implementation teams, package/PCB engineers, and CAD to ensure seamless integration. Participate in establishing review processes (layout reviews, signoff checks, and quality metrics) to ensure first-pass silicon success. Drive full-chip physical signoff, including DRC/LVS/ERC closure, EM/IR and reliability verification. Own tapeout readiness and interface with foundry and EDA partners as needed. Qualifications 5+ years of RF/analog/mixed-signal layout experience. Extensive hands-on experience with advanced FinFET process technologies (≤16nm preferred). Proven track record of top-level SoC layout integration and successful silicon tapeouts. Experience collaborating with distributed teams, including collaborating with external layout vendors. Deep understanding of RF and analog layout techniques and device physics, including high-frequency effects, parasitics, and isolation strategies. Extensive hands-on experience with power planning and full-chip physical architecture. Strong proficiency with industry-standard tools. Nice to Have Experience with high-frequency RF systems for wireless or satellite communications. Experience working on large mixed-signal SoCs with significant digital content. Exposure to reliability requirements for space or high-reliability applications. Experience developing methodologies in a high-growth environment. Compensation and Benefits: Base salary range for this role is $120,000 – $180,000 + equity in the company Salary will be based on several factors including, but not limited to: knowledge and skills, education, and expe ... (truncated, view full listing at source)