PCB Layout Design Engineer

Anduril Industries
Reston, Virginia, United StatesPosted 30 March 2026

Job Description

Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century’s most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril’s family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years. ABOUT THE TEAM Anduril Intelligence Systems (AIS) is focused on positioning Anduril as a lead provider of specialized engineering and products for Intelligence Community (IC) customers. We work within the IC to understand their requirements, shape their concepts of operation, and deliver exquisite capability across their problem set. We aim to develop and deploy critically needed capabilities that address our customers’ most pressing national security requirements. ABOUT THE JOB We are looking for a skilled and motivated PCB Layout Design Engineer to join our rapidly growing team in Reston, Virginia. In this role, you will contribute to PCB designs from concept to completion, working closely with electrical engineers on schematic design, component selection, supervision or completion of layout, bring-up, test, debug and integration with the system. WHAT YOU’LL DO Work directly with engineers to produce printed circuit board designs supporting Anduril’s products Apply modern design standards and guidelines to create high-reliability, highly manufacturable assemblies under engineering guidance Implement combinations of high-speed digital, precision analog, RF, and high-power designs Assist the team in documenting and implementing internal guidelines for design for manufacturing (DFM), design for assembly (DFA), and overall quality fabrication and assembly outputs Aid and refine team processes for PCB design, part creation, and library/database standards Coordinate external PCB design resources during design surges Work in a fast-paced environment, having to juggle multiple concurrent projects and customers REQUIRED QUALIFICATIONS Currently possesses and is able to maintain an active U.S. Secret security clearance Associates degree in electrical engineering or similar and 2+ years of professional experience in PCB Layout design Ability to read and interpret schematics and apply best practices appropriate for each design Ability to determine work priorities based on broad direction from management Proficiency in applying relevant IPC standards, CID, CID+ certification Solid understanding of PCB fabrication processes, limitations, design rules, and best practice Experience using Altium Designer CAD tools Experience with developing component libraries and library management Ability to work in team environment, taking direction and collaborating to complete designs quickly Excellent communication skills with multiple fab houses (ensuring boards are built to print) Experience with a variety of board types, including high density and high layer count (greater than 16) digital designs, power electronics, flex circuits, and RF circuits Experience with HDI (high density interconnect) and thicker boards (greater than 1.6mm) Familiar with basic signal and power integrity rules (how they affect layout) Experience with high speed digital interfaces and controlled impedance routing requirements like USB, PCIe, Ethernet PREFERRED QUALIFICATIONS Familiarity with Dense high-pin count packages (FPGA fanout). Experience designing with high speed digital interfaces, SERDES, and DDR memory structures Exposure to designing with SoC FPGA’s Experience designing with Siemens Xpedition or Cadence Allegro ECAD Tool ... (truncated, view full listing at source)
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