Hardware Engineer (onsite) - 2010267

The application window is expected to close on: 05/01/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Hardware Engineer - 2010267 *onsite at San Jose CA office* We are seeking an experienced System Level Test (SLT) Engineer to lead the design, automation, and validation of robust SLT solutions for High Volume Manufacturing (HVM) of complex, high-power, high-speed System-on-Chips (SOCs). You will play a critical role in developing and integrating automated test flows, collaborating with cross-functional teams, and ensuring seamless production test enablement and quality improvement across the product lifecycle. Key Responsibilities: Lead the design, automation, and validation of System Level Tests (SLT) tailored for HVM for cutting-edge, high-power, high-speed SOCs. Develop and integrate comprehensive test flows, scripts, and automation to maximize SLT coverage and enable seamless communication between test controllers and peripherals. Partner with system architecture, chip design, and validation teams to define production-ready SLT and HVM test solutions. Drive custom SLT development to optimize system performance, power efficiency, and test coverage for new and existing products. Oversee handler selection, enablement, and hardware integration—including PCB design, socket selection, and temperature control systems for efficient test environments. Enhance manufacturing test quality by improving test correlation, yield, and reliability across New Product Introduction (NPI), HVM, and Return Material Authorization (RMA) processes. Collaborate closely with OSATs (Outsourced Semiconductor Assembly and Test) on production enablement, sustaining operations, yield analysis, and DPPM (Defective Parts Per Million) reduction initiatives. Support silicon qualification and reliability testing (HTOL, Burn-in) at the system level to ensure robust and reliable product performance. Develop automated scripts to optimize test communication between controllers and peripherals. Lead SLT hardware integration projects, from PCB design to temperature control systems. Analyze yield data and implement improvements for higher reliability across NPI and HVM. Minimum Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. Proven experience in system-level test development, automation, and validation for high-volume SOC manufacturing. Strong background in scripting (Python, Perl, etc.) and developing automated test frameworks. Hands-on experience with test hardware integration (PCB, sockets, temperature control, etc.). Familiarity with production test flows, NPI, HVM, RMA processes, and yield analysis. Excellent cross-functional collaboration and communication skills. Preferred Qualifications: Experience working with OSATs and managing handler enablement and hardware bring-up. Knowledge of silicon qualification and reliability methodologies (HTOL, Burn-in). Expertise in power/performance optimization and DPPM reduction in production environments. Candidates should have a strong background in both test automation and hardware integration for SOC products. Experience with high-power, high-speed environments and complex SOC architectures is essential. Ability to work in a fast-paced, collaborative environment and drive initiatives independently. SiOps Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers an ... (truncated, view full listing at source)