Physical Design Lead

Job Details: Job Description: About the Foundry Technology Development Group: Foundry Technology Development (Foundry TD) is the heart and soul of Moore's Law at Intel, enabling Intel to create world-changing technology that enriches the lives of every person on earth. FTD employees drive breakthrough research, develop next generation process and packaging technologies, while also running high volume manufacturing operations in its state-of-the-art facilities. The Design Technology Platform (DTP) team in Foundry TD works closely with the technology team to maximize the value proposition of the technology for our customers thru Design Technology Co-Optimization (DTCO) and delivers the Process Design Kits (PDKs) and Foundational IP (FIP) that designers need to support their product design work and fully leverage the technology. The DTP organization scope includes technology design rules and models, technology and IP testchips, Process Design Kits (PDKs) and Foundational IP. The Role and Impact As a Physical Design Engineer, you will play a critical role in enabling customer product design through innovative use of Intel's cutting-edge process technology. Your expertise will directly impact the development of high-performance custom IP and SoC designs, enabling groundbreaking advancements in technology. By optimizing design performance and ensuring robust manufacturability, you will contribute to Intel's mission of delivering industry-leading solutions that power the future. Join us in shaping the next generation of transformative products, where your contributions will leave a lasting imprint on Intel's success and the broader technology landscape. Key Responsibilities Execute physical design implementation for custom IP and SoC designs from RTL to GDS, creating reference design databases ready for customer use. Conduct all aspects of the physical design flow, including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, and power/clock distribution. Perform verification and signoff processes such as formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity checks, layout verification, electrical rule checking, and structural design analysis. Analyze results and resolve design violations to enhance current and future product architectures. Perform placement and routing, synthesis, and Design for Test (DFT) using industry-standard EDA tools and foundry reference flows. Optimize designs to improve product parameters, including power, frequency, and area, ensuring alignment with evolving technological demands. Participate in evolving and refining physical design methodologies and automation flows to enhance efficiency and quality. Drive technical collaboration with internal teams, and EDA vendors to resolve issues and improve design productivity. Qualifications: Minimum Qualifications: Bachelor of Science degree in Electronic, Electrical, or Computer Engineering, or equivalent, with a minimum of 12 years of experience in SoC, analog, IP, or ASIC design and/or methodology development. Proficiency in running synthesis, place-and-route tools, and physical design flows, with expertise in optimization, timing convergence, IR drop analysis, DRC fixes, and low-power checks. Proficiency in static timing analysis and constraints development. Experience completing the full RTL to GDS design cycle for SOCs and Testchips, including signoff and tapeout. Skilled in Unix/Linux environments and shell programming. Solid experience in reliability verification processes. Preferred Qualifications: Master's degree in Electronic, Electrical, or Computer Engineering, or equivalent, with 10 years of relevant experience or a Ph.D. with 4 years of relevant experience. Familiarity with advanced process nodes and design methodologies. Expertise in scripting languages such as PERL and TCL for design automation. Strong problem-solving ski ... (truncated, view full listing at source)