Packaging Research and Development Engineer
IntelUS, Arizona, Phoenix$99k – $140kPosted 31 March 2026
Tech Stack
Job Description
Job Details:
Job Description:
The Role and Impact
Join Intel's Advanced Packaging Team and contribute to the Substrate Packaging Technology Development (SPTD) organization, where we strive to be the supplier of choice for leading and affordable substrate packaging. As a Packaging Module Development Engineer, you will play a pivotal role in developing innovative assembly processes and equipment that enable Intel's roadmap of future assembly packaging technologies.
This position requires most of time spent on the factory floor and/or interacting with equipment/material suppliers. The candidate will join and become part of a world class first of a kind embedded die packaging facility, learn advanced substrate manufacturing know-how, drive disruptive technology innovations, and be part of creating history in the substrate packaging industry.
Key Responsibilities
- Define and establish equipment configurations, process specifications, and integrated process flow for new process technologies
- Plan and conduct comprehensive DOEs to fundamentally characterize process window, and understand process / equipment / materials interactions
- Drive continuous process improvements on process capability/stability, quality/reliability, cost/yield, automation, and productivity
- Lead and participate in cross-functional and cross-organizational teams or work groups that support substrate technology development.
The ideal candidate should exhibit the following behavioral traits and/or skills:
- Written and verbal communication and teamwork skills.
- Interact with equipment and materials suppliers.
- Willingness to travel (some travel may be required, less than 5 percent)
- Work with ambiguity and flexibility with respect to job roles and working hours is required.
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position.
Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Knowledge and/or experience listed below would be obtained through a combination of your school work and/or classes and/or research and/or relevant previous job and/or internship experiences .
Minimum qualifications:
Master’s degree required or Bachelor’s degree with a minimum of one (1) year of relevant experience in one of the following disciplines:
Materials Science and Engineering, Chemical Engineering, Organic Chemistry, Polymer Engineering, Mechanical Engineering or any other related engineering fields
Preferred qualifications:
3 months of experience in the following:
Engineering troubleshooting and analytical skills on integrated technology issues and experience working with broad team of other process and integration engineers.
Experience owning process tools with knowledge of SPC PCS RFCs equipment troubleshooting statistical design of experiments and process development.
Experience working with a variety of organic/inorganic materials and processes as well as characterizations utilizing techniques such as DSC, TGA, D/TMA, Titration, ICPMS, FTIR, XPS, TOFSIMS, EDX, SEM, etc. is highly desirable.
Experience with statistical data analysis, JMP and JSL, Python, relational database structure and usage, machine learning.
Take the next step in your career and become a vital part of Intel's Advanced Packaging Team by applying today.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Arizona, Phoenix
Additional Locations:
Business group:
Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' ... (truncated, view full listing at source)
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