FPGA/Firmware Manager
Turion SpaceIrvine, CA$175k – $225kPosted 1 April 2026
Job Description
FPGA/Firmware Manager
Turion Space is building spacecraft for national security and in-space operations. From debris removal to space domain awareness to building a more secure space economy, we are a team focused on getting real hardware to orbit fast and scaling capability.
We are looking for an FPGA/Firmware Manager to lead our rapidly growing team in Irvine, CA. In this role, you will manage a high performing team responsible for creating the architecture, end-to-end design and verification of projects FPGA/SOC systems. This role will guide team growth as well as establish robust documentation and procedures.
This is a full-time, exempt position based on-site at our Irvine, California headquarters.
Responsibilities
- Manage and mentor a small team of direct reports
- Own development of HDL and firmware on custom FPGA, FPGA SoC and low-level embedded systems
- Provide early guidance and input on architecture decision for subsystem and vehicle-level architectures
- Define requirements and processes to ensure traceability and progress tracking
- Contribute to custom HDL modules for FPGA systems (focus on high speed data movement and handling)
- Design firmware for soft cores (MicroBlaze, RISC-V, etc.) platforms to interface with FPGA fabric and peripherals
- Write custom HDL to interface with SoC hard cores, drivers and corresponding custom firmware.
- Work with electrical engineers and others to support the bring-up of custom hardware
- Establish performance goals, conduct reviews, and foster a culture of innovation and accountability
- Lead verification of HDL and firmware to ensure flight-readiness
Qualifications
Required Qualifications
- 8+ years of experience developing firmware, or, HDL for FPGAs in a professional environment
- 2+ years of experience managing an engineering team
- Bachelor’s degree in Electrical Engineering, Computer Science, Mathematics, or related field
- Demonstrated work in RTL design using VHDL, Verilog, and/or SystemVerilog
- Proficiency with FPGA design tools (Xilinx Vivado, Microchip Libero, or similar)
- Experience developing firmware in bare-metal or RTOS environments
- Experience developing embedded systems using C/C++
- Strong understanding of digital design and embedded systems principles
- Ability to obtain a Secret and/or TS/SCI security clearance
Preferred Qualifications
- Interest in mentoring and developing engineering talent
- Experience with high-level synthesis (HLS) tools (e.g. Xilinx Vitis HLS, MATLAB FPGA generator)
- Experience with FPGA verification techniques (formal verification, UVM, SystemVerilog assertions)
- Familiarity with Xilinx Ultrascale, Zynq MPSoC, Versal, and/or Microchip PolarFire platforms
- Proficiency working with firmware development tools such as JLink, Keil, IAR, or GCC
- Experience with FreeRTOS and embedded Linux.
- Strong understanding of FPGA timing, floor planning, and clock domain crossing best practices
- Experience with AMBA bus architectures (AXI, AHB, APB) and custom AXI IP design
- Experience with high-speed serial interfaces (GbE, PCIe, Aurora, LVDS) and low-speed interfaces (RS422, UART, I2C, SPI)
- Familiarity with RAM architectures, efficient buffering techniques, and FLASH interfaces (ONFi)
- Experience with image sensors and camera systems
FPGA Manager / Firmware Manager / Hardware Manager: $175,000 – $225,000 USD.
ITAR Requirements:
This position may include access to technology and/or software source code that is subject to U.S. export controls. To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.
Benefits:
We offer a comprehensive compensation and benefits package designed to support the well-being and professional growth of our e ... (truncated, view full listing at source)
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