Mixed Signal Logic Design Engineer

Job Details: Job Description: Develops the logic design, register transfer level (RTL) coding, and simulation for DDRPHY IP. Participates in the definition of architecture and microarchitecture features and improvements of the block being designed. Define power intent strategy, handling of signals crossing power planes and clock domains, along with other FE collateral for integration. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Drive and ensure IP handoff quality and compliance Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. 8 years of RTL coding and/or IP integration experience. IP/Subsystem architecture, I/O architecture, industry standard high speed bus protocols, including JEDEC Good integration knowledge of analog circuits and mixed signal designs. Create or understand logic functionalities in terms block diagrams, data flow diagram, algorithm state machine, finite state machines, and detailed timing charts. Implement RTL in SystemVerilog, perform unit level testing and debug tests. Integrate hard IP and soft IPs including industry standard and proprietary interfaces. Industry exposure and knowledge of design methodology Perform RTL Lint check, RTL synthesis, Equivalence checking, CDC checking, power crossing checking and support Static Timing Analysis. Tcl/Tk/Perl/Python to automate design flow and improve efficiency Ensure designs are delivered on time and with the highest quality by using proper checks. Resolve technical issues in developing digital blocks, gate level simulation, power and static timing analysis with team members. Work with verification team for test plan/strategy to meet all functional requirements and performance. Work with timing and physical team for timing closure and meet power and area goals. Support project managers with effort estimations and resource planning. Support team leader in coaching, training and development team members. Strong written and verbal communication skill. Able to communicate well with counterparts and key stakeholders including cross-site partners. Experience/knowledge in DDR design is strong advantage Knowledge of Synthesis/Auto P and R, Primetime, post-silicon testing, etc. are a plus. Job Type: Experienced Hire Shift: Shift 1 (Malaysia) Primary Location: Malaysia, Penang Additional Locations: Business group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any ... (truncated, view full listing at source)