ADCE Packaging Design Architect

Job Details: Job Description: We're looking for a motivated, passionate, and talented Engineer to join Intel's Advanced Design Customer Enabling (ADCE) group within Assembly Packaging Technology manufacturing organization (APTM) to realize Intel's vision with advanced packaging technologies. In this position, you will be responsible for defining Package and Disaggregation Architecture across Intel's product portfolios (CPUs, Chipsets, SOC designs and more) as part of the Advanced Design Group.  The candidate will be responsible for working with the Si, Package and Board design teams to define and implement a co-design strategy which would optimize product performance and cost at the package and system level. The job will require the candidate to understand silicon and packaging technology development FMEAs and product packaging requirements - both physical and electrical. You will work closely with Intel and external customers on advanced design nodes to establish design flows for advanced package architecture. You will be directing technical aspects of the Silicon Bridge/ Interposer and Package Architecture process including conducting early route studies, creation of specifications, providing guidance for electrical analysis and supervision of production layouts. You will collaborate with EDA partners on advancing design tools and identify most efficient design methods and will serve as the technical expert on advanced package architectures and design tools as well as consult on design and implementation issues. The candidate will have a good technical understanding in the areas of Si -Package - Board interaction. An ideal candidate would exhibit behavioral traits that indicate: Should be a self-motivated engineer who has strong technical background in design and electrical analysis. The candidate should be a self-motivated engineer who has strong technical background in both design and electrical analysis. They will work with a cross functional team including silicon IP design, package and PCB platform to define and co-optimize package solutions. This position determines creative design approaches and solutions based on formal education and judgement, works with the design and layout teams to implement those solutions Strong analytical ability and problem-solving skills like: identifying, isolating, and debugging issues and providing creative solutions. Ability to work independently and at various levels of abstraction. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications: Bachelor's with 8 years or master’s with 6 years or PhD with 4 years in electrical engineering or Chemical Engineering or Mechanical Engineering or Material Science. 5 years of experience in semiconductor fabrication and packaging 6 years and in-depth knowledge/background in Package, PCB design, or IC digital design. 5 years of experience with design and electromagnetic simulation tools: Mentor, Cadence tools, SPICE, Ansys tools 3 years of Experience in Cadence Allegro platform tools (PCB Editor, Advanced Package Designer, APD/SiP, Concept HDL, Sigrity), and/or Mentor Xpedition platform tools (PCB Layout/XPD, Designer, Hyperlynx). Preferred Qualifications: Strong analytical ability and problem-solving skills: identifying, isolating, and debugging issues and providing creative solutions. Ability to work independently and at various levels of abstraction Strong organization, time management, and communication skills, self-motivated Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Arizona, Phoenix Additional Locations: US, ... (truncated, view full listing at source)