Full-Chip Physical Design Engineer

Meet the Team Step into Cisco's ASIC Physical Design Team, where innovation meets collaboration. As a group of highly skilled engineers, we're redefining what's possible in silicon technology. Our mission is to drive the future of chip design, managing full-chip physical implementation from RTL to GDSII and beyond. Working hand-in-hand with Front-End teams, we transform cutting-edge designs into industry-leading silicon solutions. Together, we're building the foundation for the future of connectivity, driving advancements in power, performance, and reliability with every project. Your Impact Drive Cisco's silicon innovation by creating breakthrough solutions that blend hardware and software to empower people worldwide. Execute top-level RTL to GDSII implementation and signoff to ensure the delivery of high-quality, reliable silicon. Perform critical physical design tasks, including gate-level netlist synthesis, floorplanning, and routing, while applying advanced Clock Tree Architectures like Mesh and H-Tree. Optimize designs to achieve industry-leading power, performance, and area (PPA) metrics while maintaining design integrity through formal verification. Collaborate with multi-functional teams to accelerate design processes and deliver impactful technology that shapes the future of connectivity. Minimum Qualifications Bachelor's or Master's degree in Electrical Engineering or Computer Science. Minimum of 3 years of experience in ASIC design and verification. Experience in deep submicron CMOS technologies. Comprehensive knowledge of the full design cycle from RTL to GDSII. Preferred Qualifications Experience in RTL2GDS flow, floorplanning, and power planning. Proficiency in PnR tools such as Synopsys or Cadence. Strong scripting skills for automation and efficiency improvements. Experience with chip-level design planning, partitioning, and feedthrough management. Ability to collaborate with IP teams for the physical integration of analog IPs. Experience working with multi-functional teams (package and power integrity) to ensure successful bump and PG planning. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.