Chip Level STA ASIC Engineer

Meet the Team Join Cisco’s ASIC Physical Design Team, where we ensure the highest quality in full-chip timing closure and circuit performance to guarantee a successful tape-out. We bridge the gap between design and reality by collaborating across block implementation, flow, SDC, EMIR, and IP/tool vendor teams to drive silicon excellence. As a tight-knit group of highly skilled engineers, we foster a collaborative environment where innovation meets precision. Together, we are building the foundation for the future of connectivity, driving advancements in power, performance, and reliability with every project. This is your opportunity to shape the technology that connects the world while working alongside a team that values mentorship and celebrates technical success. Your Impact Drive Cisco’s silicon innovation by leading full-chip partitioning and implementation from initial floorplan to final tape-out to ensure high-quality silicon delivery. Execute complex chip-level planning, including clock structures and feedthrough management, to optimize power, performance, and area (PPA) metrics. Collaborate with cross-functional teams, including package, power integrity, and RTL design, to resolve integration challenges and ensure seamless handoffs. Conduct rigorous quality checks and sign-off procedures to guarantee design integrity before the silicon is sent to manufacturing. Foster a culture of technical excellence and mentorship to accelerate design processes and empower global connectivity. Minimum qualifications Bachelor's or Master's degree in Electrical Engineering or Computer Science. Minimum of 3 years of hands-on experience in ASIC design and verification. Proven experience working with deep submicron CMOS technologies. Comprehensive knowledge of the full design cycle from RTL to GDSII. Demonstrated hands-on experience in RTL2GDS flows, floorplanning, and power planning. Preferred qualifications Proficiency in industry-standard PnR tools such as Synopsys or Cadence. Strong scripting skills to drive automation and efficiency improvements. Experience with the physical integration of analog IPs and chip-level clock structures. Ability to identify and communicate fixes for non-physical aware connections. Excellent collaboration skills for working effectively with diverse cross-functional teams and external vendors. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.