Senior Density Fill Development Engineer
Intel4 Locations$150k – $285kPosted 2 April 2026
Job Description
Job Details:
Job Description:
Embark with us on a journey of growth and transformation as we create exceptionally engineered technology and bring AI everywhere. As a valued team member, your adaptability and attention to detail will contribute to our drive for results and relentless pursuit of quality, ensuring we meet our customers' needs with precision.
Join us and build on our legacy of innovation and collaboration as we deliver world‑changing technology that improves the life of every person on the planet.
Life at Intel: https://jobs.intel.com/en/life-at-intel
Join Intel's Design Technology Platform (DTP) organization and become an integral part of a highly skilled team driving the development of cutting-edge technologies. As an EDA Tools Software Engineer, you will design, develop, test, and debug software tools and methodologies that directly support Intel's hardware product design and manufacturing processes. Your work will enable design teams to innovate faster, meet complex manufacturability constraints, and deliver industry-leading products to market. By contributing to Intel's advanced process technologies, you will play a pivotal role in achieving leadership in design automation and fostering a culture of innovation.
Key responsibilities include but are not limited to:
Design, develop, and debug Fill components of Process Design Kits (PDKs)
Provide algorithmic solutions using tools such as Calibre, ICV, and Pegasus to address density deficiencies and ensure manufacturability compliance.
Collaborate with process developers, design rule owners, and end users to define requirements and implement state-of-the-art solutions. - Automate workflows to enhance efficiency, accuracy, and deployment across design teams.
Develop comprehensive test cases and systems to validate software tools and ensure seamless integration with various design methodologies.
Innovate and drive advancements in EDA tools and methodologies to meet the evolving needs of Intel's technology ecosystem.
Partner with cross-functional teams and external EDA vendors to define and implement new tool features and methodologies.
Maintain documentation, including training materials and user guides, to support customers and ensure robust deployment.
The candidate should exhibit the following traits:
Proven track record of collaborating across multiple internal and external teams to deliver optimal solutions.
Exceptional analytical and problem-solving skills with the ability to address cross-disciplinary challenges.
Strong written and verbal communication skills, with the ability to present complex technical concepts clearly.
Leadership experience driving innovation, process improvements, or cross-functional initiatives.
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research, and relevant previous job and/or internship experience.
Minimum Qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 8 years of relevant experience, Master's degree with 6 years of relevant experience, OR PhD with 3 years of relevant experience. in:
Proficiency in scripting languages such as Python, Tcl, or Perl for automation
Expertise in EDA tools, including Calibre, ICV, or Pegasus, with strong skills in developing and debugging rule decks (e.g., SVRF/TVF, PXL, PVL/PVTCL).
Solid understanding of semiconductor device physics, process technology, and design rules.
Experience in developing algorithmic solutions for physical design challenges in advanced manufacturing nodes.
Strong knowledge of Unix/Linux platforms and computing environments.
Preferred Qualifications:
Experience with advanced physical verification techniques, including DRC, and density/fill modules.
Familiarity with custom layout tools such as Cadence ... (truncated, view full listing at source)
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