Packaging Research and Development Engineer

Intel
US, Arizona, Phoenix$115k – $163kPosted 2 April 2026

Job Description

Job Details: Job Description: Substrate Packaging Technology Development (SPTD) is looking for a Packaging Research and Development Engineer to join the Module Engineering Backend Area specifically to be in charge of process and material development Client/Server product substrate technology development and to scale EMIB substrate packaging technology to enable further die disaggregation / heterogenous integration. This position requires most of time spent on the factory floor and/or interacting with equipment/material suppliers. The candidate will join and become part of a world class first of a kind embedded die packaging facility, learn advanced substrate manufacturing know-how, drive disruptive technology innovations, and be part of creating history in the substrate packaging industry. Responsibilities will include but not be limited to: - Define and establish equipment configurations, process specifications, and integrated process flow for new process technologies - Plan and conduct comprehensive DOEs to fundamentally characterize process window, and understand process / equipment / materials interactions - Drive continuous process improvements on process capability/stability, quality/reliability, cost/yield, automation, and productivity - Lead and participate in cross-functional and cross-organizational teams or work groups that support substrate technology development. The ideal candidate should exhibit the following behavioral traits and/or skills: - Written and verbal communication and teamwork skills. - Interact with equipment and materials suppliers. - Willingness to travel (some travel may be required, less than 5 percent) - Work with ambiguity and flexibility with respect to job roles and working hours is required. Qualifications: You must possess the below minimum qualifications to be initially considered for this position.Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Minimum qualifications: Candidates should meet one of the following qualifications: Bachelor’s degree in Materials Science and Engineering, Chemical Engineering, Organic Chemistry, Polymer Engineering, Mechanical Engineering, or a related field with 3 years of semiconductor industry experience, or Master’s degree in Materials Science and Engineering, Chemical Engineering, Organic Chemistry, Polymer Engineering, Mechanical Engineering, or a related field with 2 years of semiconductor industry experience, or PhD degree in Materials Science and Engineering, Chemical Engineering, Organic Chemistry, Polymer Engineering, Mechanical Engineering, or a related field Preferred qualifications: 1 years of experience in the following: - Engineering troubleshooting and analytical skills on integrated technology issues and experience working with broad team of other process and integration engineers. - Experience owning process tools with strong knowledge of SPC PCS RFCs equipment troubleshooting statistical design of experiments and process development. - Experience working with a variety of organic/inorganic materials and processes as well as characterizations utilizing techniques such as DSC, TGA, D/TMA, Titration, ICPMS, FTIR, XPS, TOFSIMS, EDX, SEM, etc. is highly desirable. - Experience with statistical data analysis, JMP and JSL, Python, relational database structure and usage, machine learning. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Arizona, Phoenix Additional Locations: Business group: Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ... (truncated, view full listing at source)
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