Packaging Module Development Engineer
IntelUS, Arizona, Phoenix$134k – $220kPosted 2 April 2026
Job Description
Job Details:
Job Description:
The Advanced Packaging Technology Manufacturing (APTM) division at Intel is responsible for the development and commercialization of industry-leading semiconductor packaging technologies for mobile, edge, and hyperscale computing platforms. Within APTM, the Assembly Technology Development (ATD) team pioneers innovative package assembly solutions and scales them for high-volume manufacturing.
The Packaging Module Development Engineer will contribute to advancing technology and foundry capabilities by:
• Developing First, Second, and Mid-Level Interconnect (FLI, SLI, MLI) and thermal interface solutions to support Intel's future packaging platforms.
• Collaborating with multifunctional and cross-organizational teams to optimize assembly processes for quality, reliability, cost, yield, productivity, and manufacturability.
• Innovating next generation materials, equipment, and fabrication processes to enhance semiconductor packaging capabilities at scale.
• Managing projects to meet product development timelines.
• Applying formal education and judgment to solve technical problems.
• Providing sustaining support for equipment performance and process health in high-volume manufacturing.
• Responding promptly to foundry customer requests and events.
The ideal candidate will demonstrate:
• Technical leadership, strategic planning, and critical thinking.
• Ability to coach and develop technical teams.
• Tolerance for ambiguity and adaptability in a dynamic environment.
• Flexibility in managing changing priorities and responsibilities.
• Experience leading teams in a highly matrixed organization.
• Initiative and ability to work independently.
• Strong communication, influencing, technical, and analytical skills.
This position requires regular onsite presence.
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position.
Preferred qualifications are in addition to the minimum qualifications and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork, classes, research, relevant previous job, and/or internship experiences.
Minimum Qualifications
Master's Degree with at least 5 years of experience packaging/module development, advanced packaging, semiconductor processing, and system integration.
Preferred Qualifications
One or more years of experience in any of the following:
• PhD with one or more years in Materials Science, Mechanical Engineering, Electrical Engineering, Physics/Applied Physics, or a related field.
• At least one publication in a peer-reviewed technical journal.
• Technology development, including familiarity with Statistical Process Control (SPC) and/or Design of Experiments (DOE).
• Delivering results for complex, time-critical technical projects.
• Semiconductor fabrication processes and technology.
• Previous related work experience in a semiconductor foundry.
Join us in this dynamic and impactful role where your expertise will drive innovation and define the future of semiconductor packaging. Be part of Intel's mission to create technology that enriches the lives of every person on Earth.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Arizona, Phoenix
Additional Locations:
Business group:
Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing ar ... (truncated, view full listing at source)
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