ASIC Design Engineering Technical Lead (Hybrid)

The application window is expected to close on: 05/29/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . This position requires that you live within commuting distance of our San Jose, CA office and commute to the office 4-5 days per week. MEET THE TEAM Cisco Silicon One (#CiscoSiliconOne) is a business organization with a long track record of building complex and high-performance Silicon ASICs. Our silicon devices drive the world’s most complex networks and carry over 90% of IP traffic. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. We are a highly specialized ASIC team with experts in all aspects of Front-End design including the development of programmable, scalable silicon architectures that power next-generation networking products.. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry! YOUR IMPACT Define, design and take end to end Front-End ownership of ASIC subsystems to be deployed in a range of Cisco platforms. Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products. Help define the process, methods, and tools for design and implementation of complex developments. Work on some of the most challenging problems in high-performance silicon for hyperscale infrastructure. Design and implement high-frequency, high-performance RTL in Verilog / System Verilog, meeting aggressive timing, power, and area targets. Lead design specifications and technical reviews, ensuring architectural clarity and high-quality implementation. Drive technical execution across architecture, design, verification, and physical implementation teams to deliver robust silicon. Collaborate closely with verification and physical design teams to close functional coverage, timing, and integration challenges. Mentor engineers and elevate engineering rigor, design quality, and technical execution across the team. Lead debug and root-cause analysis across simulation, system bring-up, and post-silicon validation. Creates re-usable code that promotes efficiencies in new ways Influence system architecture and key design decisions across complex ASIC subsystems. MINIMUM QUALIFICATIONS Bachelor's degree in Electrical Engineering with 8 years of ASIC design experience, or Master's degree in Electrical Engineering with 6 years of ASIC design experience, or PhD in Electrical Engineering and 3 years of ASIC design experience. ASIC design experience, delivering silicon from microarchitecture, specification, and RTL coding through tape-out with multiple ASIC tape-outs at advanced technology nodes. Strong expertise in high-performance RTL design using Verilog/SystemVerilog. Deep understanding of timing closure, power optimization, and clock gating techniques. Experience with ASIC development flows including simulation, synthesis, and static timing analysis. PREFERRED QUALIFICATIONS 10 years of ASIC design experience, delivering silicon from architecture and specification through tape-out. Strong documentation, problem-solving, debug and technical communication skills Experience working cross-functionally and collaborating with various technical teams Problem solver who loves to tackle new challenges and a self-starter who is highly motivated and thrives on innovative technology. Strong communicator in a team setting, enjoys working in a dynamic team environment, and is an out-of-the-box thinker. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyon ... (truncated, view full listing at source)