Junior Physical Design Engineer

Meet the Team Step into Cisco's ASIC Physical Design Team, where innovation meets collaboration. As a group of highly skilled engineers, we're redefining what's possible in silicon technology. Our mission is to drive the future of chip design, managing full chip physical implementation from RTL to GDSII and beyond. Working hand-in-hand with Front-End teams, we transform cutting-edge designs into industry-leading silicon solutions. Here, you'll have the opportunity to shape tomorrow's technology, driving advancements in power, performance, and reliability with every project. Together, we're building the foundation for the future of connectivity. Your Impact Drive Cisco's silicon innovation by executing precise Clock Tree Synthesis (CTS) and optimization to ensure robust clock distribution across advanced semiconductor designs. Perform transistor-level SPICE simulations to validate timing, power, and signal integrity, ensuring all clock circuits meet stringent performance targets. Analyze clock skew, latency, and jitter to implement effective solutions that resolve timing violations and enhance design reliability. Develop automated scripts using TCL, Python, or Shell to streamline clock analysis and simulation flows, improving overall design efficiency. Collaborate with RTL, STA, and layout teams to achieve seamless timing closure and deliver high-quality silicon solutions that empower global connectivity. Minimum Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field. Minimum of 2 years of hands-on experience in VLSI Physical Design or Circuit Design. Demonstrated expertise in Clock Tree Synthesis (CTS) concepts and clock distribution networks. Experience with industry-standard SPICE simulation tools such as HSPICE, Spectre, or FineSim. Practical experience with EDA tools including Cadence Innovus, Synopsys PrimeTime, or Cadence Virtuoso. Preferred Qualifications Experience with low-power design techniques and advanced clock gating strategies. Exposure to EM/IR analysis and power grid considerations. Understanding of process variation and Monte Carlo SPICE simulations. Experience in full-chip physical design flows. Proven track record in advanced technology nodes (e.g., 7nm, 5nm, or 16nm). Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.