Memory Chip Design Engineer

The job opening is for a full-time Research Staff Member in the Design Group in Western Digital's research department. The role will be a part of a multi-functional team whose aim is to develop and eventually commercialize Western Digital's strategic radiation hardened memory technology.  The responsibilities for the role will include: Developing high density memory chip custom layout Including shared operational circuitry along with at pitch line drivers All phases of chip design layout to be included: From architecture definition, density and performance optimization, final verification up to and including tape out Running and Debugging Physical Verification flows including DRC, LVS, ERC and Antenna Checks Minimize parasitic resistance and capacitance (R and C) in critical paths to meet timing and power consumption specifications Comprehend and address reliability engineering issues such as electromigration, IR Drop and Design For Manufacturing robustness Coordination of a Split-Fab Design and Development between WD (for Memory Array Layers) and a CMOS Foundry (for Operational Circuitry) Developing and Harmonizing CMOS Foundry wafer requirements to allow for continued processing of Memory Array layers in WD’s Fabrication Line Development of EDA Tool Design Rules for WD’s Memory Array Layers Defining and executing the split-fab tape out flow Minimum of a Bachelor's, Master's or PhD degree in Electrical Engineering, Physics, or closely related field. The prior track record of a viable candidate must show: Previous design layout, tape out and validation of high density memory chip designs Capability to develop design layout schedules that meet chip functional requirements and timelines Proficiency in Cadence Virtuoso (VXL), Mentor Graphics Calibre, or Synopsys IC Validator Capability to work closely with circuit designers to iterate on schematics and with process engineers to understand fabrication constraints Deep understanding of CMOS fabrication processes, Phase-Shift Mask Development and Multi-Patterning Techniques The following skills and experiences are highly desired Experience developing memory cell models for inclusion in simulation tool environment, such as Verilog-A Experience with emerging memories such as MRAM, ReRAM, or PCM Experience developing Radiation Tolerant Layouts Track record of publications and patents related to memory design layout WD is committed to providing equal opportunities to all applicants and employees and will not discriminate against any applicant or employee based on their race, color, ancestry, religion (including religious dress and grooming standards), sex (including pregnancy, childbirth or related medical conditions, breastfeeding or related medical conditions), gender (including a person’s gender identity, gender expression, and gender-related appearance and behavior, whether or not stereotypically associated with the person’s assigned sex at birth), age, national origin, sexual orientation, medical condition, marital status (including domestic partnership status), physical disability, mental disability, medical condition, genetic information, protected medical and family care leave, Civil Air Patrol status, military and veteran status, or other legally protected characteristics. We also prohibit harassment of any individual on any of the characteristics listed above. Our non-discrimination policy applies to all aspects of employment. We comply with the laws and regulations set forth in the " Know Your Rights: Workplace Discrimination is Illegal ” poster. Our pay transparency policy is available  here .   WD thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. ... (truncated, view full listing at source)