Static Timing Analysis (STA) Methodology Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a STA methodology engineer who owns timing across advanced-node, high-performance, low-power designs, bringing deep expertise with PrimeTime, noise/crosstalk/OCV analysis, and strong scripting skills. They will lead the development and optimization of end-to-end STA methodologies and flows, drive data- and ML-assisted timing automation, and partner closely with logic, physical design, DFT, and EDA vendors to solve complex timing challenges across multiple IPs and products. This role is hybrid, based out of Santa Clara, CA, Austin, TX, or Fort Collins, CO. We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting Who you are An experienced Static Timing Analysis (STA) / timing methodology engineer with a BS/M in Electrical or Computer Engineering (or equivalent experience) 5+ years in industry, focused on high-performance and low-power designs at advanced technology nodes. As well as a deep knowledge of STA tools and techniques, including noise, crosstalk, and OCV analysis. You are fluent with PrimeTime and related signoff tools (e.g., PT-SI, PTPX, PT-ECO) and have extensive hands-on experience driving signoff correlation, advanced static timing analysis, and signoff closure. You are strong at debugging timing constraints, resolving timing correlation issues, and developing effective timing closure strategies. You write robust, production-quality scripts in Tcl, Python, and/or Perl and are comfortable building and maintaining CAD utilities and flow components. What we need A senior methodology owner to lead cross-functional efforts to solve complex timing challenges across multiple IPs, projects, and technology nodes. Experience developing and enhancing STA methodologies across the full RTL-to-GDS flow, including: Early timing estimation and timing feasibility checks. Timing optimization techniques in synthesis and place-and-route. Timing signoff methodologies and criteria. Post-route timing ECO strategies and execution. A technical leader to architect, optimize, and maintain production STA flows using industry-standard EDA tools, continuously improving PPA (Power, Performance, Area) and runtime efficiency. A methodology engineer who can explore and deploy data-driven and ML-assisted techniques to: Improve STA automation. Predict and prioritize timing risk. Guide optimization strategies across blocks and full-chip. Design, implement, and maintain scalable CAD utilities and STA flow components that improve PPA, robustness, and team productivity. A methodology owner who continuously refines workflows and introduces new technologies to ensure robust, PPA-optimized timing solutions across all product lines. What you will learn How to scale STA methodologies across a diverse portfolio of IP and SoC programs, balancing aggressive performance targets with strict power and area constraints. Best practices for integrating data-driven and ML-assisted approaches into timing flows to improve automation, predictability, and decision-making. How to influence tool roadmaps by partnering closely with leading EDA vendors on advanced-node timing, noise, and variability challenges. How to operate within and help shape a r ... (truncated, view full listing at source)