ASIC Physical Design Engineer

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we’re mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space. The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today’s and tomorrow’s massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits. With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we’d love for you to apply. The Role We are seeking a ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full physical design flow—from synthesis to GDSII—working closely with architecture, RTL, verification, and packaging teams. You’ll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space. Responsibilities Execute the complete physical design flow for complex SoC blocks and/or top-level integration, including synthesis, floorplanning, place route, CTS, STA, and physical verification. Perform timing closure and optimization across multiple corners and modes using industry-standard tools. Collaborate with DFT teams to ensure clean timing convergence. Develop and maintain scripts and automation to improve flow efficiency and consistency. Support physical sign-off activities including DRC/LVS, STA, EM, Signal Integrity and power analysis. Assist in chip-level integration, timing and functional ECOs, and tapeout preparation. Contribute to methodology development, tool evaluation, and flow documentation. Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 2+ years of experience in ASIC physical design for complex SoCs. Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent). Strong understanding of timing analysis, power optimization, and physical verification flows. Experience with hierarchical or flat SoC design methodologies. Familiarity with FinFET technologies. Working knowledge of DFT, UPF/CPF power intent, and ECO implementation. Strong problem-solving skills and ability to work cross-functionally in fast-paced environments. Nice to Have Exposure to radiation-hardened or space-qualified ASICs. Experience with chip-package co-design or advanced packaging (2.5D/3D). Familiarity with physical design service vendor management or offshore collaboration. Experience with sign-off through TSMC. Experience with Gate-All-Around technologies. Experience working in cross-functional, geographically distributed teams. Compensation and Benefits ... (truncated, view full listing at source)