Member of Technical Staff - Microarchitect / RTL Design

Member of Technical Staff - Microarchitect / RTL Design ABOUT ARCHITECT Architect is a frontier AI lab for chip design. We build AI models and tools for on-demand custom ASICs at scale. Our goal is to co-design custom ASICs alongside evolving ML workloads, and enable a new era of domain-specific chips that unlock capabilities impossible with current hardware paradigms. Born out of Stanford Research, our team blends AI with Silicon with a founding team from Anthropic, Google DeepMind, Meta SuperIntelligence, xAI, Apple and Intel. WHAT YOU'LL DO As a Founding Member of the Technical Staff on the RTL Design team at Architect, you'll own the AI-driven microarchitecture and RTL design going into production silicon. - Review and monitor AI-explored microarchitectural specifications into production SystemVerilog RTL for AI core blocks: PE/MAC arrays, scratchpad memory controllers, SRAM banks and arbiters, DMA engines, and datapath logic. - Own AI-driven RTL flow end-to-end from code through lint, CDC, synthesis, and timing closure. - Work directly with the NPU architect to refine microarchitectural specs, resolve implementation trade-offs, and feed area/timing/power realities back into the architecture and internal AI systems. - Define and maintain interface specifications (AXI, AXI-Stream) for block- and subsystem-level integration. - Build and maintain RTL infrastructure for AI-driven flow: design automation scripts, regression flows, lint/CDC waivers, and integration collateral. - Support DV bring-up with reference models, assertions, and architectural documentation for verification closure. - Support FPGA prototyping on Xilinx for early functional validation. WHAT WE'D LIKE TO SEE Qualifications & Skills: - Degree: Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a closely related field. - Tapeout Experience: 5+ years (10+ preferred) in RTL design with at least one advanced-node tapeout. - Domain Background: RTL design experience on NPU, ML accelerator, or processor IP — ideally having worked on Apple Neural Engine, Qualcomm Hexagon NPU / AI Engine, Google Edge TPU, AMD XDNA, Samsung NPU, MediaTek APU, NVIDIA DLA blocks, or accelerators at Groq, Cerebras, MatX, d-Matrix, or similar. - SystemVerilog: Clean, synthesizable, lint-clean RTL with strong design habits — parameterization, modularity, reuse. - Block-Level Depth: Hands-on experience with compute datapaths (MAC arrays, vector units, accumulators), on-chip SRAM controllers and arbiters, DMA engines, or scratchpad memory management. - SoC Methodology: Solid grasp of synthesis, timing constraints, clock domain crossings, reset strategies, and AMBA protocols (AXI, AHB, APB). - Python: Strong skills for design automation, regression infrastructure, and tooling. - PPA Ownership: Experience taking a block from RTL through synthesis and working with PD teams on timing/area/power closure. - Leadership: Ability to lead RTL design efforts and grow into a team lead over time. Bonus: - Low-power design techniques: clock gating, power gating, multi-voltage domains, UPF. - FPGA prototyping experience (ideally Xilinx Vivado/Vitis). - Familiarity with SIMD/VLIW execution pipelines or instruction-driven datapath design. - Experience writing SVA assertions and functional coverage for design-side verification. - Prior IP-team experience on DMA controllers, memory subsystems, interconnects, or similar SoC infrastructure blocks. WHAT WE OFFER - Competitive salary and meaningful equity stake - Fast-paced startup with autonomy and visible impact - Cutting-edge challenges at the intersection of AI and silicon design