Silicon Packaging Design Engineer

Job Details: Job Description: The Role and Impact: Intel is seeking a motivated and innovative Layout Design Engineer to join our team of world-class semiconductor professionals. In this role, you will be at the forefront of designing the physical layout of of Intel's silicon that are used for its packaging technology. You will collaborate with customers, electrical engineers (for signal integrity and power delivery) to optimize performance, reliability, and manufacturability, driving innovation and efficiency across our cutting-edge products. As a Layout Design Engineer, you will play a critical role in ensuring Intel's continued leadership in the semiconductor industry, contributing to advanced methodologies and groundbreaking solutions. Key Responsibilities: Develop custom layouts for Intel's silicon used for its packaging technology. Perform detailed physical array planning, area optimization, and signal and power routings. Design and verify standard cell libraries, ensuring compliance with design rules, PDK specifications, and reliability requirements. Execute layout verification processes, including checks for electron migration, voltage drop (IR), self-heat, ESD, and other reliability metrics. Use custom auto-routers and placers to efficiently construct layouts and optimize designs. Troubleshoot design, tool, and methodology issues related to layout construction. Provide feedback to circuit design engineers on feasibility studies and implement circuit enhancement requests. Develop and drive innovative layout methodologies to improve productivity, quality, and manufacturability. Utilize EDA tools and design flows for floor planning, routing, reliability verification, and performance optimization. Collaborate with cross-functional teams to ensure seamless execution of silicon tape-in. Qualifications: Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. 4 years of experience in layout design with a Bachelor's degree; 3 years with a Master's degree; or 0 years with a PhD. Proficiency in using Cadence Virtuoso Layout Suite and other industry-standard EDA tools. Strong understanding of analog device and metal layout fundamentals, design for manufacturing (DFM), and reliability verification processes. Experience in layout construction, debugging, and full-chip top metal/analog routing design. Familiarity with tape-in assembly, route methodologies, and performance verification for layout. Preferred Qualifications: Demonstrated ability to solve complex technical problems and troubleshoot tool and methodology issues. Knowledge of floor planning tools and flows, library integration, and design archiving processes. Effective communication skills to collaborate with cross-functional teams and provide feedback to circuit design engineers. Ability to execute disciplined design processes and align work to Intel's core values and performance standards. We invite you to bring your expertise and creativity to Intel, where you can contribute to industry-shaping innovation while growing your career in a supportive, inclusive, and dynamic environment. Job Type: Experienced Hire Shift: Shift 1 (Malaysia) Primary Location: Malaysia, Penang Additional Locations: Business group: Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, an ... (truncated, view full listing at source)