Intel Process Integration Engineer - (FE)
Intel2 Locations$104k – $199kPosted 21 April 2026
Job Description
Job Details:
Job Description:
Join Intel and build a better tomorrow.
What we do: The Intel Foundry MDCE and Logic Technology development (LTD) organizations delivers process technology innovation to drive Intel's product roadmap.
What we offer:
• We give you opportunities to transform technology and create a better future by delivering products that touch the lives of every person on earth.
• As a global leader in innovation and new technology, we foster a collaborative, supportive, and exciting environment where the brightest minds in the world come together to achieve exceptional results.
• We offer a competitive salary and financial benefits such as bonuses, life and disability insurance, opportunities to buy Intel stock at a discounted rate, and Intel stock awards (eligibility at the discretion of Intel Corporation).
• We provide benefits that promote a healthy, enjoyable life: excellent medical plans, wellness programs, and amenities, time off, recreational activities, discounts on various products and services, and many more creative perks that make Intel a Great Place to Work.
• We give you opportunities to transform technology and create a better future by delivering products that touch the lives of every person on earth.
Benefits:
We provide benefits that promote a healthy, enjoyable life: excellent medical plans, wellness programs, and amenities, time off, recreational activities, discounts on various products and services, and many more creative rewards that make Intel a Great Place to Work Find more information about our amazing benefits here.
The ideal candidate should exhibit behavioral traits that indicate:
Job Responsibilities include but are not limited to:
1. Process Flow Development
• Develop and define integrated front end process flows for new technology nodes.
• Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams.
• Establish process windows and integration schemes.
2. Yield and Defect Reduction
• Analyze yield loss and parametric failures.
• Perform root cause analysis using statistical tools (SPC, DOE, FMEA).
• Drive corrective actions to improve yield and cycle time.
3. Device Performance Optimization
• Ensure electrical parameters meet design targets.
• Work closely with device engineers to tune process conditions.
• Optimize critical dimensions (CD), overlay, and film thickness.
4. Process Control and Monitoring
• Implement control plans and process monitoring strategies.
• Use statistical tools such as: Cpk / Ppk, Control charts, Capability analysis
5. Technology Transfer
• Support ramp from RnD to high-volume manufacturing (HVM).
• Document process specifications and standard operating procedures (SOPs).
6. Cross-Functional Collaboration/Work with
• Device Engineering
• Equipment Engineering/Module Engineering
• Yield Engineering
• Reliability Teams
• Design Teams
Qualifications:
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
•Candidate must possess a PhD degree in one of these fields: Electrical Engineering, Physics, Applied Physics, Optics, Material Science, Chemical Engineering, Mechanical Engineering, or related discipline.
•Candidate must possess at least one of the following:
6 months experience on one or more of the following areas:
o Semiconductor device fabrication or nanotechnology.
o Electrical characterization of transistors or other semiconductor devices.
o Clean room process development.
Preferred Qualifications:
• JMP, MATLAB, Scripting languages (1.e. Python, JSL, TCL), or programming languages (1.e. SQL, C/C).
• Strong understanding of Device physics (CMOS, FinFET, GAA, etc)
• Hand on experience in VLSI device fabrication and testing in the lab.
• Knowledge of basic VLSI fabrication instruments (1.e. mechanism of dry etcher, ALD (atomic ... (truncated, view full listing at source)
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