Mechanical Engineering Technical Leader

Cisco
3 Locations$169k – $241kPosted 31 May 2026

Tech Stack

Job Description

The application window is expected to close on: 05/31/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . This role can be performed onsite in San Jose, CA or remotely within the US. Meet the Team We are seeking a highly experienced and driven ASIC Mechanical Engineer to join the Cisco ASIC Group. In this role, you will lead mechanical and thermomechanical simulation efforts for ASICs and complex silicon/package/board assemblies, driving design decisions and ensuring product reliability for high-performance Cisco systems. You will work across a globally distributed team and play a key role in shaping simulation methodologies, reliability strategies, and design guidelines across packaging, board-level integration, and system hardware engineering. Your Impact Lead and perform advanced finite element analysis (FEA) to evaluate thermomechanical behavior and reliability of ASIC packages and board-level assemblies, including stress, warpage, and interconnect integrity. Own and drive solder joint reliability assessments, including thermal cycling, mechanical shock, and vibration, and develop lifetime prediction methodologies. Model and analyze nonlinear and time-dependent material behavior, including creep, viscoplasticity, and fatigue, with strong understanding of temperature and rate effects. Define and establish simulation methodologies, modeling best practices, and correlation strategies for packaging and board-level reliability. Drive correlation between simulation and reliability testing (e.g., TCT, drop, field returns) to improve predictive accuracy and enable design signoff. Influence product design by providing data-driven recommendations, risk assessments, and reliability sign-off criteria early in the development cycle. Lead root cause analysis for mechanical/reliability failures and guide cross-functional teams toward robust solutions. Develop and scale simulation workflows and automation using Python, Fortran, or similar tools to improve team efficiency and consistency. Communicate complex technical findings clearly to stakeholders across mechanical, packaging, and system teams. Minimum Qualifications Bachelors 8 years, or Masters 6 years, or PhD 3 years in mechanical engineering or related field. Strong experience in thermomechanical simulation of semiconductor packages and/or board-level assemblies. Proven track record in solder joint reliability analysis, including fatigue and/or creep modeling. Deep hands-on experience with ABAQUS or ANSYS, including nonlinear material modeling. Demonstrated ability to drive technical decisions and work across global teams. Preferred Qualifications Expertise in board-level reliability (BLR) and PCB–package interaction modeling. Professional with solder constitutive models (e.g., Anand) and fatigue life prediction methods (Coffin-Manson, Darveaux). Knowledge of JEDEC/IPC standards for reliability qualification. Experience with advanced packaging (flip chip, 2.5D/3D, heterogeneous integration). Track record of correlating simulation with test data and driving design improvements. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our ... (truncated, view full listing at source)
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