ASIC Physical Design Technical Lead

The application window is expected to close on: 07/21/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms powering Cisco’s core Switching, Routing, and Wireless products. We design networking hardware for enterprises, service providers, the public sector, and nonprofit organizations worldwide. As part of the team behind Cisco Silicon One—the industry’s only unified silicon architecture spanning top-of-rack switches to web-scale data centers—you’ll help shape Cisco’s groundbreaking solutions by designing, developing, and testing some of the most advanced ASICs in the industry. Your Impact Fullchip Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning; Handson experience with Fullchip clock mesh and Flex-HTree methods RTL-to-GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks with a focus on performance, power and die size optimization. Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements. Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow teams to enable best-in-class design methodology. Proficiency in low-power design methodologies using UPF Work with Foundry and standard cell IP vendors to define the signoff methodologies and validate/adjust them when you receive feedback from Post-Silicon Validation teams Experience in using AI tools to improve productivity Minimum Qualifications Bachelor’s Degree in Electrical Engineering with 8 years of Physical Design experience or Master’s Degree in Electrical Engineering with 6 years of Physical Design experience, or PhD in Electrical Engineering with 3 years of Physical Design experience. Experience working on Fullchip activities. Experience with RTL2GDSII flow and design tapeouts in 7nnm/5nm/3nm or below process technologies. Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre/Pegasus. Preferred Qualifications Experience with hierarchical design, timing closure, physical design convergence, and power integrity analysis. Experience with static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions. Experience in Fullchip floor-planning and power grid planning. Experience with custom clock (H-Tree or Mesh) at chip level. Experience with Python and usage of AI tools by giving accurate prompts Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: The starting salary range posted for this position is $183,800.00 to $263,600.00 and reflects the projected salary range for new ... (truncated, view full listing at source)