Physical Design Engineer II (Full Time) - United States

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Applications accepted until further notice. Meet the Team Acacia, part of Cisco, provides innovative silicon-based high-speed optical interconnect products to accelerate network scalability through advancements in performance, capacity, and cost. Our DSP ASICs, silicon photonic PICs, and coherent modules empower cloud and service providers to meet the fast-growing demand for data. We have assembled a team of multi-functional experts capable of solving the challenges of next-generation optical interconnects, resulting in industry-leading, award-winning products. Come join us at Cisco, named the #1 world’s best workplaces, and do purposeful work that makes a global impact and gives back to a company culture that empowers an inclusive future for all. Your Impact As a Physical Design Engineer with Acacia, you will focus on the technical execution of high-performance ASIC designs. Working as an individual contributor, you will own the RTL-to-GDSII implementation flow for advanced semiconductor nodes, ensuring that Acacia’s networking platforms meet rigorous power, performance, and area (PPA) targets. You will be responsible for the successful delivery of assigned blocks from specification through to tapeout . Implement end-to-end RTL-to-GDSII implementation for advanced nodes (sub-7nm) Perform floor planning, place and route, and clock/power distribution Conduct static timing analysis (STA) and drive timing closure for multi-mode/multi-corner designs Manage the physical design of assigned blocks, ensuring quality and consistency to project timelines Collaborate with the Physical Design team to debug and resolve complex physical implementation issues Implement ECO strategies and support sign-off processes Contribute to the refinement of design methodologies and standard processes within the engineering team Document and track progress for assigned project achievements ​ Minimum Qualifications Completion, within the past 3 years, or current enrollment with expected completion within 12 months,  a  Bachelors 2 years of relevant experience) or Masters 0 years of relevant experience . Relevant fields include Electrical Engineering, Computer Engineering, Computer Science, or a closely related field. Hands-on experience in ASIC physical design and implementation. Working knowledge with hierarchical floorplanning , clock and power distribution, global signal and I/O planning along with physical convergence, timing closure, and hierarchical design methodology . Understanding power integrity and EMIR analysis. ​ Preferred Qualifications Experience with Scripting using languages such as TCL, Perl, Python, etc. Place & Route experience using tools such as Cadence Innovus or Synopsys ICC2. Experience formal equivalence check, timing closure, EMIR, physical verification DRC/LVS Experience with block level EMIR closure. Physical Verification experience including tools such as Synopsys ICV or Mentor Calibre . Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our ... (truncated, view full listing at source)