Physical Design Engineer - CPU Core

Intel
US, California, Folsom$106k – $200kPosted 23 April 2026

Job Description

Job Details: Job Description: Intel's Silicon Engineering Group seeks a CPU Core Physical Design Engineer to work on the physical implementation of cutting-edge processor designs from RTL to manufacturing-ready GDS. This role requires experience in physical design methodologies and CPU-specific design challenges to deliver world-class, high-performance, low-power processors that power Intel's industry-leading products. Key Responsibilities Physical Design Implementation Execute complete physical design flow for custom CPU designs from RTL to GDS, creating manufacturing-ready design databases Perform synthesis, place and route, clock tree synthesis, floorplanning, and power/clock distribution for complex CPU cores Conduct static timing analysis, reliability analysis, and power/noise analysis for high-performance processor designs Optimize CPU designs to improve critical product parameters including power, frequency, and area Verification & Signoff Execute comprehensive verification and signoff processes including formal equivalence verification and static timing analysis Perform reliability verification, static and dynamic power integrity analysis, and layout verification Conduct electrical rule checking (ERC) and structural design checking to ensure manufacturing compliance Ensure design quality and manufacturability across all verification domains CPU-Specific Expertise & Optimization Apply specialized knowledge in CPU structural and physical design including physical clock design and timing closure Perform coverage analysis, multiple power domain analysis, structured placement, and routing optimization Implement design-for-test (DFT) methodologies specific to CPU architectures Collaborate closely with logic, circuit, architecture, and design automation teams to optimize microarchitectures Technology Leadership & Innovation Work with industry EDA vendors to build and enhance tool capabilities for high-speed, low-power synthesizable CPU design Analyze design results and provide recommendations to improve current and future CPU microarchitectures Participate in development and improvement of physical design methodologies and flow automation Drive adoption of advanced design techniques and emerging technologies Qualifications: The Minimum qualifications are required to be initially considered for this position.  Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or STEM-related field of study 2 years of experience in VLSI circuit design and synthesis 1 years of experience in static timing analysis 1 years of experience in low power design methodologies Experience with physical design EDA tools (i.e. Synopsys, Cadence, Mentor Graphics) Experience with timing closure, power optimization, and signal integrity analysis Preferred Qualifications Postgraduate degree (Master's/PhD) in Computer Engineering, Computer Science, Electrical Engineering, or STEM-related field of study Experience with x86 CPU architecture and Intel processor designs Experience with Tcl, Perl, Python Programming Experience in CPU microarchitecture and high-performance design principles What We Offer Competitive compensation and comprehensive benefits Opportunity to work on industry-leading CPU architectures and technologies Access to cutting-edge EDA tools and advanced process technologies Collaboration with world-class CPU architects and design engineers Professional development and career advancement opportunities Direct impact on products powering global computing infrastructure Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primar ... (truncated, view full listing at source)
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