Analog Circuit Design Engineer

Job Details: Job Description: About the Team The Design Technology Platform (DTP) is one of the key pillars-alongside Technology and Development and Foundry-enabling Intel to deliver winning products. Our mission is to enable product design teams to reach market faster with leadership products on cutting-edge technologies. Role Summary As a member of the Advanced Design Foundation IP group in DTP, you will be at the forefront of designing critical foundational collateral on leading edge Intel processes to meet density and performance scaling goals of Intel CPU and SoC products. ADFIP serves as the design interface with the process development team working out key design process interactions for all new processes. These collaterals include Metal Finger Capacitors (MFC), Thin Film Resistors (TFR), inductors, varactors, transmission lines, and other passive components. You will collaborate closely with process/device, PDK/modeling, EDA, and product design teams to co-optimize design and technology (DTCO) and to deliver silicon proven solutions through test chips. What You'll Do Your responsibilities will include, but are not limited to: You will be responsible for driving on-time library PDK release with highest quality, coordinate with the design owners and multiple stake holders in device, integration, OPC, DR, and runset for customer solutions. Ensure the timely development and test coverage to cover possible design usage scenarios for passive component templates. Definition of copy exact foundational IP in collaboration with analog and RF designers in product groups and AD to support passive component needs while optimizing for performance, area, and process compatibility. Working with process device and reliability stake holders as part of DTCO to co-optimize design, process modeling and design rules for passive components. Designing library collateral schematics and layouts for passive components, and characterizing them through all PV RV and electrical parameter extraction flows. Develop and maintain template design guidelines and best practices for MFC, TFR, and other passive components across different process nodes. Collaborate with modeling teams to ensure accurate electrical models for designed templates. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Bachelor's degree in electrical engineering or related STEM field with 4 years in analog/RF circuit design or device physics fundamentals. OR Master's degree in electrical engineering or related STEM field with 3 years in analog/RF circuit design or device physics fundamentals. OR Ph.D. degree in electrical engineering or related STEM field with 6 months of professional experience in analog/RF circuit design or device physics fundamentals. 3 years' experience with SPICE level circuit design/simulation and Cadence Virtuoso (or equivalent custom design environment), including layout generation. 3 years' experience in data analysis/scripting (e.g., Python or Matlab). Preferred Qualifications: 1 year of experience with device physics, analog fundamentals (gain, bandwidth, noise, linearity, stability), and/or variability/yield (corners, mismatch, Monte Carlo). Experience with passive component design and characterization (capacitors, resistors, inductors) Knowledge of electromagnetic simulation tools and RF design principles Familiarity with advanced process technologies and their impact on passive component performance Experience with Verilog modeling, EM/IR and reliability checks, or electromagnetic/RF simulation flows. Familiar with Pcell design using SKILL Exposure to post silicon characterization and debug Familiarity with statistics/DOE and machine learning for design space exploration or correlation Comfortable working across ... (truncated, view full listing at source)