Physical Design Engineering Manager

Job Details: Job Description: The Role and Impact We are seeking a highly skilled Physical Design Engineering Manager to lead and inspire a passionate team of physical design engineers responsible for delivering cutting-edge semiconductor designs. In this role, you will be at the forefront of enabling Intel's success by overseeing complex processes, from RTL to GDS, and driving innovation in physical design implementation, optimization, and verification. Your leadership will play a pivotal role in ensuring product architecture excellence, timely execution, and continuous improvement for current and future technologies. Join us to shape the future of computing and leave a lasting impact on Intel's mission to create world-changing technology. Key Responsibilities Direct and manage a team of physical design engineers responsible for chip, subsystem, or block-level implementation, including clocking, timing, and integration. - Provide technical guidance on physical design processes, including power delivery, place-and-route, clock tree synthesis, and optimization techniques. Oversee the development of complex layout integrated circuit designs, simulation designs, RTL to GDS flows, and logic synthesis. Review and analyze circuit layout architectures, prototypes, and documentation for SoC development. Ensure issue resolution during physical design verification flows and recommend fixes for violations at the block and chip levels. Drive execution through clear goal setting, accountability, and performance management to meet schedule and landing zone requirements for physical design projects. Facilitate a productive team environment by inspiring engagement, developing capabilities, and modeling Intel's values. Ability to build and lead effective teams, drive results through others, and manage performance with disciplined execution. Excellent communication skills and a proven track record of developing others and fostering engagement. Execute projects successfully while maintaining accountability and productivity. Qualifications: Minimum Qualifications: Bachelor's degree in a relevant field and at least 6 years of experience, or a Master's degree with 4 years of experience, or a PhD with 2 years of experience. Experience physical design tools and methodologies, including RTL to GDS flows, SoC integration, and tape-in assembly. Physical design optimization, place-and-route, clock tree synthesis, and power delivery experience. Experience managing SoC physical design verification flows and resolving design violations. We invite you to bring your expertise, leadership, and innovation to Intel, where you will contribute to shaping the future of technology. Apply today to join us in driving excellence while advancing the boundaries of semiconductor design. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Texas, Austin Additional Locations: US, California, Santa Clara, US, Colorado, Fort Collins, US, Massachusetts, Beaver Brook, US, Oregon, Hillsboro Business group: At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military an ... (truncated, view full listing at source)