GPU Design Verification Engineer
IntelUS, California, Folsom$106k – $200kPosted 24 April 2026
Job Description
Job Details:
Job Description:
The Role and Impact
Are you passionate about cutting-edge computer graphics and excited to contribute to the technology that powers millions of devices worldwide? Join Intel's Graphics IP team as a GPU Design Verification Engineer, where you will play a pivotal role in ensuring the functional accuracy and performance of Intel's leading-edge GPU architectures. This position provides an opportunity to collaborate with a world-class team of architects, designers, and engineers to deliver next-generation graphics solutions. Your work will directly impact Intel's mission to redefine how the world experiences technology, driving innovation across integrated, discrete, and AI-enabled graphics platforms.
Key Responsibilities
Develop scalable and reusable IP verification plans, test benches, and architectures for graphics logic components, including 3D graphics, media, and display.
Execute verification plans and run system simulation models to validate design, analyze power and timing, and identify bugs.
Debug and resolve failing tests in the pre-silicon environment, root cause issues, and implement corrective measures.
Collaborate with architects, RTL developers, and physical design teams to enhance verification methodologies and meet functional, performance, and power goals.
Write specifications for design enhancements and code design changes in RTL while adhering to coding guidelines.
Analyze timing reports to optimize design approaches for frequency requirements.
Develop functional/code coverage goals and ensure coverage closure to maintain high-quality design standards.
Interface with emulation and software teams to align RTL validation efforts.
Contribute to process improvements and gain domain expertise for independent validation execution.
Qualifications:
Minimum Qualifications
Bachelor's degree in electrical/computer engineering, Computer Science, or a related STEM field with 3 years of relevant experience, or a master's degree with 2 years of experience, or a PhD in related field.
Experience in System Verilog and UVM methodologies.
Experience in testbench development, feature verification, coverage execution, and assertion-based verification.
Experience Python or similar scripting languages.
Expertise in RTL design and debugging using industry-standard tools and methodologies.
Preferred Qualifications
Experience GPU or CPU architecture, including computer architecture fundamentals.
Debug experience in frontend design and verification flows, tools, and methodologies.
Prior exposure to IP development teams and verification strategies.
Familiarity with programming languages such as C, C, and object-oriented programming.
Working knowledge of scripting languages like Perl, Ruby, or Python.
Effective problem-solving, debugging, and communication skills.
Be a part of Intel's journey to engineer the future and deliver innovations that shape the world. Apply now to drive meaningful technology advancements with us.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, California, Folsom
Additional Locations:
Business group:
At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origi ... (truncated, view full listing at source)
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