GPU Design Verification Engineer

Job Details: Job Description: We are looking for a seasoned professional GPU Design Verification Engineer to join our GPU IP team. In this role, you will be responsible to Plan, design complex structures, lead the design and verification efforts of complex logic blocks and features. You will be responsible for defining design and verification strategy, architecting testbenches. Key Responsibilities Planning, Designing complex architecture designs meeting all performance criteria, Verification strategies and leading complex projects and debugging. Work closely with architects and micro-architecture teams to define functional verification strategies and execute comprehensive test plans. Develop scalable and reusable IP verification plans, test benches, and architectures to meet graphics microarchitecture specifications. Independently own the development of test environments, feature verification, and functional coverage closure. Perform debugging and issue replication, root cause analysis, and corrective action in pre-silicon environments. Validate design functionality by executing system simulations, analyzing power and timing, and uncovering bugs. Utilize assertion-based verification techniques to strengthen reliability metrics. Collaborate with GPU design and verification teams to enhance infrastructure and methodologies for continuous improvement. Drive technical reviews and documentation of verification strategies and plans. Effective communication skills, teamwork abilities, and a mindset of continuous learning. Expert knowledge of the GPU pipeline Mastery of Verilog, System Verilog, and Logic Synthesis for high-frequency, low-power designs Thorough understanding of cache coherency, memory interfaces, etc. Ability to work independently and manage complex tasks with minimal supervision. Qualifications: Minimum Qualifications Bachelor's degree in electrical engineering, Computer Engineering, Computer Science, or related field, plus 3 years of relevant experience; or Master's degree with 2 years of relevant experience; or PhD with 1 years of relevant experience. 4 years in ASIC Design and verification. Experience in the following: System Verilog coding and UVM verification Assertion-based verification methodologies Industry standard protocols such as AMBA, PCIe, USB, etc. Simulation tools (VCS, Xcelium, Questa) Constrain random testing and assertions Leading teams, mentoring juniors and driving milestones. Simulation debugging, code coverage closure, and functional coverage analysis. Preferred Qualifications Experience in high performance data center, AI tools or advanced process nodes. Contribution to industry standards Proficiency in Python or similar scripting languages Familiarity with silicon bring up and post- silicon debugging. Proficiency in C/ C Expertise in architecting plans for complex IP structures Expert experience in the development of feature verification test benches and execution of functional coverage closure. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Folsom Additional Locations: Business group: At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national or ... (truncated, view full listing at source)