Quality and Reliability R&D Lab Engineer
IntelUS, Oregon, Hillsboro$134k – $189kPosted 28 April 2026
Job Description
Job Details:
Job Description:
About Intel Foundry
At Intel Foundry, our Technology Development and Manufacturing teams power a worldwide network of cutting edge fabs and assembly/test facilities. To keep pace with an aggressive technology roadmap, we are pushing the limits of transistor and interconnect reliability delivering faster time to data and higher quality insights that directly shape Intel's and our foundry customers' most advanced process technologies.
The Opportunity
Join the Stress Testing and Reliability (STaR) Lab as part of the Foundry Lab Network (FLN), within the broader Foundry Quality, Reliability, and Labs (FQRL) organization. You'll help develop and enable efficient, high-quality reliability testing, with hands-on exposure to reliability characterization of transistors, interconnects, and other devices on today's and tomorrow's technology nodes.
Location: Intel's Ronler Acres campus in Hillsboro, Oregon—just outside Portland in the beautiful Pacific Northwest, offering an outstanding quality of life alongside world-class engineering challenges.
What You'll Do
As a Quality and Reliability R&D Lab Engineer in Intel's Reliability Labs, you will be at the center of enabling the reliability data collection that underpins our most advanced process technologies. In this role, you will own, develop, and manage a suite of lab tools ensuring they are fully maintained, production ready, and capable of delivering high quality, data.
Core Responsibilities:
Technical Problem Solving: Drive root cause investigations when issues arise
Continuous Improvement: Lead improvement projects that enhance data integrity, tool performance, automation, and overall lab efficiency
Capability Development: Design, develop, and qualify new tools, test methodologies, and workflows for characterizing device reliability
Cross-functional Collaboration: Work closely with lab operations, industrial engineers, module engineers, and external vendors
Documentation & Transfer: Ensure new processes and methods are robustly developed, documented, and smoothly transferred to operations
Development Focus Areas:
Design and qualify new reliability stress techniques for transistors, and interconnects
Build next-generation reliability stress infrastructure including hardware, software, procedures, and documentation
Support pathfinding, technology development, and certification milestones for Intel and foundry customers
Model world-class safety, quality, and operational excellence
The successful candidate must demonstrate the following:
Proven verbal and written communication skills
Team player with proven skills to collaborate and influence in heterogenous team
Proven skills to perform successfully in a fast paced, high pressure team environment
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Note:
For information on Intel’s immigration sponsorship guidelines, please see
Intel U.S. Immigration Sponsorship Information
Minimum Qualifications and Experience :
A minimum of a Master's degree in Electrical Engineering/Physics/related field with 3 years of experience on electrical characterization of electronic materials and devices.
In addition, you must have 3 years of experience in the following:
Experience in semiconductor electrical characterization, device testing, and troubleshooting using parametric analyzers, oscilloscopes, and related equipment
Leadership experience in technical organizations
Project management skills
Statistics with practical experience using JMP
Experience applying statistical analysis techniques to experimental data; proficiency with JMP or equivalent
Experience with hardware automation, preferably using LabVIEW, TestStand, or Python
Preferred Qualifications and Experience :
PhD in Electrical E ... (truncated, view full listing at source)
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