Senior Manager Digital Hardware Engineering, FPGA & PCB Design

<div class="content-intro"><p>Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century’s most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril’s family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years.</p></div><h4>WHAT YOU’LL DO</h4> <ul> <li>Lead an electrical engineering team in creating embedded compute solutions for vehicle management, DSP, and networking</li> <li>Own the full PCB development cycle of host boards for FPGAs / SoCs / SoMs (Developing requirements, schematic capture, board layout, bring-up, test, and integration)</li> <li>Develop and improve workflows throughout the FPGA / HDL design cycle (Architecture, functional block definition, simulation, system testing, HDL library standardization)</li> <li>Collaborate with internal stakeholders to develop a strategy for developing and rolling out your compute solutions across Anduril in a scalable manner</li> <li>Create, maintain and communicate product development schedules with sufficient detail to ensure that all assigned personnel are aware of their tasks and deadlines.</li> </ul> <h4>REQUIRED QUALIFICATIONS</h4> <ul> <li>Bachelor’s Degree in Electrical Engineering or equivalent</li> <li>7+ years of experience designing, testing and troubleshooting complex board designs in military, automotive or similar hardware.</li> <li>Experience with leading an Electrical Engineering team focused on Digital Design</li> <li>Proficiency in an HDL language (VHDL, Verilog)</li> <li>Familiarity with common MCU, CPU, FPGA devices and technologies.</li> <li>Familiarity with standard interfaces such as Ethernet, CAN, I2C, SPI, PCIe, USB, etc.</li> <li>Experience in design for signal integrity / power integrity.</li> <li>Knowledge of modern analog and digital electronics and electronic circuits.</li> <li>Competence with test equipment such as oscilloscopes, logic analyzers, thermal chambers, current-probes, and automation of tests.</li> <li>Proficient with Altium Designer or equivalent electronic design automation design tool</li> <li>Eligible to obtain and maintain an active U.S. Top Secret security clearance</li> </ul> <h4>PREFERRED QUALIFICATIONS</h4> <ul> <li>Understanding and familiarity with DO-254, DO-178C, DO-160, DO-311A</li> <li>Understanding and familiarity with MIL-STD-810, MIL-STD-704, MIL-STD-461</li> <li>Expertise in computer networking</li> <li>Experience with implementing enhanced security measures</li> </ul><div class="content-pay-transparency"><div class="pay-input"><div class="title">US Salary Range</div><div class="pay-range"><span>$170,000</span><span class="divider"></span><span>$255,000 USD</span></div></div></div><div class="content-conclusion"><p><span data-contrast="auto">The salary range for this role is an estimate based on a wide range of compensation factors, inclusive of base salary only. Actual salary offer may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations. Highly competitive equity grants are included in the majority of full time offers; and are considered part of Anduril's total compensation package. Additionally, Anduril offers top-tier benefits for full-time employees, including:</span><span data-ccp-props="{"134233117":false,"134233118":false,"335551550":0,"335551620":0,"335559738":240,"335559739":240}"> </span></p> <p><strong><span data-contrast="auto">Healthcare Benefits </span></strong></p> <ul> <li><strong><span data-cont ... (truncated, view full listing at source)