Senior Formal Verification Engineer

<div class="content-intro"><p>Waymo is an autonomous driving technology company with the mission to be the world's most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver—The World's Most Experienced Driver™—to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver powers Waymo’s fully autonomous ride-hail service and can also be applied to a range of vehicle platforms and product use cases. The Waymo Driver has provided over ten million rider-only trips, enabled by its experience autonomously driving over 100 million miles on public roads and tens of billions in simulation across 15+ U.S. states.</p></div><p data-pm-slice="1 1 []"><em><span data-sheets-root="1">Waymo's Compute Team is tasked with a critical and exciting mission: We deliver the compute platform responsible for running the fully autonomous vehicle’s software stack. To achieve our mission, we architect and create high-performance custom silicon; we develop system-level compute architectures that push the boundaries of performance, power, and latency; and we collaborate closely with many other teammates to ensure we design and optimize hardware and software for maximum performance. We are a multidisciplinary team seeking curious and talented teammates to work on one of the world’s highest performance automotive compute platforms. </span></em></p> <p data-pm-slice="1 1 []"><em>This role follows a hybrid work schedule and you will report to a Silicon Engineering Lead.</em></p> <p><strong>You will:</strong></p> <ul> <li>Define and drive formal strategy for first-pass silicon success. Own the formal verification sign-off approach across complex IP and SoC designs, utilizing advanced formal techniques (e.g., Bounded Model Checking, Datapath Validation, Connectivity, Sequential LEC, etc.)</li> <li>Architect robust and scalable FV environments. Develop and deploy reusable formal testbenches, methodology flows, and high-coverage SVA assertion suites for systemic deployment across multiple design blocks and projects</li> <li>Technical leadership mentorship. Serve as the team's formal Subject Matter Expert, training and guiding logic designers and verification engineers to effectively incorporate formal methods into their workflows</li> <li>Strategic planning and test plan execution. Collaborate with Architecture and Design teams to translate complex system and IP specifications into comprehensive formal verification test plans</li> <li>Drive FV Infrastructure Reporting. Maintain and enhance continuous integration, regression flows, and dashboarding to provide clear, actionable formal verification status and sign-off metrics to leadership</li> <li>Advanced bug-hunting and debugging. Apply state-of-the-art formal techniques (e.g., assume-guarantee, abstractions, reductions) to tackle and efficiently decompose the most challenging, intractable verification problems</li> </ul> <p><strong>You have:</strong></p> <ul> <li>BS/MS/PhD in CS/EE or related field, combined with 5+ years of hands-on formal verification experience on shipping silicon products</li> <li>Deep, expert-level proficiency with at least one major commercial formal verification platform (e.g., Cadence JasperGold, Synopsys VC Formal, Mentor Questa Formal)</li> <li>High level language proficiency in C++ and/or Python</li> <li>Ability to model complex designs in SystemVerilog and advanced SystemVerilog Assertions, including writing complex cut-points and environment models for effective formal proof convergence</li> <li>Proven track record in applying advanced formal debug techniques for problem decomposition (e.g., clock domain crossings, abstractions, assume-guarantee reasoning)</li> <li>Excellent verbal and written communication skills with the ability to influence cross-functional teams (Design, Architecture, Software) and drive technical alignment</li> </ul> <p><strong>We prefer:</stron ... (truncated, view full listing at source)