Chiplet Physical Design Engineer

<div class="content-intro"><p>Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.</p></div><p>As a Senior Chiplet Physical Design Engineer at Tenstorrent, you will work on a high-profile, cutting-edge program designing and integrating multiple chiplets into a System-in-Package (SiP). You’ll collaborate closely with Tenstorrent experts and leaders across the USA, Japan, and other global sites, as well as external partners, to deliver world-class CPU and AI silicon. In this role, you will own critical aspects of synthesis and place-and-route for high-speed CPU core designs, contributing directly to performance, power, and area outcomes on advanced process nodes.</p> <p>This role is<strong> </strong>remote, based out of The United States.</p> <p>We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.</p> <p> </p> <p><strong>Who You Are</strong></p> <ul> <li>An experienced physical design engineer who thrives in complex, multi-stakeholder projects.</li> <li>Detail-driven, with a strong sense of ownership from synthesis through design closure.</li> <li>Comfortable working at advanced nodes (3nm and below) and multi-GHz designs.</li> <li>A collaborative team player who enjoys mentoring others and influencing methodology.</li> <li>Clear communicator who can balance technical depth with schedule and resource constraints.</li> </ul> <p> </p> <p><strong>What We Need</strong></p> <ul> <li>Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or Computer Science.</li> <li>10+ years of industry experience in physical design for CPU, or GPU products.</li> <li>Strong hands-on experience with Synopsys and/or Cadence tools across synthesis, PR, and closure.</li> <li>Proven expertise in timing closure, ECO flows, and PV convergence at block and chip level.</li> <li>Proficiency in scripting (TCL required; Python or similar strongly preferred) and strong English communication skills.</li> </ul> <p> </p> <p><strong>What You Will Learn</strong></p> <ul> <li>How large-scale chiplet-based systems are architected, implemented, and integrated into SiP solutions.</li> <li>Best practices for achieving timing and power convergence on advanced silicon technologies.</li> <li>How physical design decisions impact system-level performance and scalability.</li> <li>Effective collaboration across global teams and external partners.</li> <li>How Tenstorrent evolves and standardizes physical design methodologies across projects.</li> </ul> <p> </p> <p><em>Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.</em></p> <p><em>Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.</em></p><div class="content-conclusion"><p><em>This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Coun ... (truncated, view full listing at source)