Staff Analog Design Engineer

<div class="content-intro"><p>Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.</p></div><p>Tenstorrent is seeking a Staff Analog/Mixed Signal Design Engineer to join our Analog Design team. In this role, you’ll develop differentiated die-to-die chiplet PHY IP solutions including PLL’s.</p> <p>This role is<strong> remote </strong>role open to any location in the <strong>U.S.</strong></p> <p>We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.</p> <p> </p> <p><strong>Who you are</strong></p> <ul> <li>A Staff Analog/Mixed-Signal Design Engineer to develop die-to-die chiplet PHY IP, including PLLs and key analog/mixed-signal blocks in deep sub-micron FinFET technologies.</li> <li>A hands-on owner for the full lifecycle: design, verification, layout interaction, tape-out, and silicon bring-up to production quality.</li> <li>A strong cross-functional partner who can work with architecture, analog, digital, verification, layout, and software teams to integrate and optimize AMS IP.</li> </ul> <p> </p> <p><strong>What we need</strong></p> <ul> <li>BSEE/MSEE/PhD with 10 years of relevant analog/mixed-signal IC design experience, including PLL and AMS design in FinFET processes.</li> <li>Proficient with industry-standard EDA tools and comfortable working closely with layout, with a solid grasp of layout-driven constraints and impacts.</li> <li>Experienced with circuit/SoC tape-outs that reached production, and confident in silicon bring-up and testing.</li> <li>A collaborative, data-driven engineer—able to clearly analyze, document, and present results, with a self-motivated, energetic approach to building and improving AMS IP.</li> <li>Background in high-speed datacomm/SerDes and die-to-die PHY design.</li> <li>Experience with circuits such as bias generators, amplifiers, LDOs, switched-cap circuits, oscillators, ADCs, DACs, Tx/Rx sub-circuits, and DDR/PCIe/USB PHY components.</li> <li>Familiarity with high-speed digital (serializer/deserializer, dividers) and Tx/Rx equalization (de-emphasis, CTLE, DFE).</li> </ul> <p> </p> <p><strong>What you will learn</strong></p> <ul> <li>How to push the limits of die-to-die chiplet PHY IP in advanced FinFET nodes, from architecture through high-volume production.</li> <li>How to co-optimize analog, digital, and layout to hit aggressive performance, power, and area targets in complex SoCs.</li> <li>Deeper expertise in high-speed I/O and PHY architectures, plus practical methodologies for scalable, reusable AMS IP across multiple products.</li> </ul> <p> </p> <p><em>Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.</em></p> <p><em>Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.</em></p> <p><em>This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. </em></p><div class="content-conclusion"><p><em>This offer of employment is contingent upon the applicant being eligible to access U.S. expo ... (truncated, view full listing at source)