Staff Product Development Engineer - ATE Content Developer

Tenstorrent
Austin, Texas, United States; Santa Clara, California, United States$100k – $500kPosted 24 February 2026

Job Description

<div class="content-intro"><p>Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.</p></div><p><span style="font-size: 10pt;">Tenstorrent is looking for a Staff Product Development Engineer - ATE Content Developer, who will be focused on core content development for high-performance AI/ML silicon. They will be responsible for developing production test programs on ATE test platforms, translating DFT/ATPG content into optimized ATE solutions, and implementing Streaming Scan Network (SSN) architectures for efficient test data delivery. High level challenges include reducing test cost while maintaining coverage targets, optimizing test time for chiplet and multi-die architectures, and enabling rapid yield learning through robust test methodologies. The work is done collaboratively with a group of highly experienced engineers across DFT, design, product, and manufacturing domains.</span></p> <p><span style="font-size: 10pt;">This role is hybrid, based out of <strong>Austin, TX </strong>or <strong>Santa Clara, CA.</strong></span></p> <p><span style="font-size: 10pt;">We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.</span></p> <h2><span style="font-size: 10pt;"><strong>Who You Are</strong></span></h2> <ul> <li style="font-size: 10pt;"><span style="font-size: 10pt;">An experienced semiconductor test engineer with 7 years and a BS/MS in EE/ECE/CE and a track record testing complex digital devices on advanced nodes.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Hands-on with Advantest V93K and/or Teradyne UltraFlex+ platforms, comfortable owning production test programs end‑to‑end.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Deeply familiar with DFT/ATPG flows and test architectures: scan chains, MBIST, compression, JTAG/IEEE 1149.1, and common fault models (stuck‑at, transition, path delay, cell‑aware).</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Proficient in C/C++ or Java, with strong scripting skills in Python, Perl, or TCL to automate flows, pattern handling, and data analysis.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Skilled at debugging across ATE hardware, test programs, and silicon, and at using data to drive root‑cause analysis and yield improvement.</span></li> </ul> <h2><span style="font-size: 10pt;"><strong>What We Need</strong></span></h2> <ul> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Develop and optimize production test programs on Advantest V93K using the SmarTest 8 environment, from bring‑up through high‑volume manufacturing.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Translate ATPG patterns (STIL/WGL) into production‑ready test content, balancing test time, coverage, and cost for chiplet and multi‑die AI/ML devices.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Implement and debug Streaming Scan Network (SSN) based content for high‑speed scan delivery, ensuring robust and scalable scan test infrastructure.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Own test content for scan, BIST, and memory test structures, collaborating with DFT teams on pattern debug, ... (truncated, view full listing at source)