Principal Architect
Motorola SolutionsHo Chi Minh, VietnamPosted 25 February 2026
Job Description
Company Overview At Motorola Solutions, we believe that everything starts with our people. We’re a global close-knit community, united by the relentless pursuit to help keep people safer everywhere. We build and connect technologies to help protect people, property and places. Our solutions foster the collaboration that’s critical for safer communities, safer schools, safer hospitals, safer businesses, and ultimately, safer nations. Connect with a career that matters, and help us build a safer future. Department Overview We are building a unified, high-performance software foundation that powers Intelligent Edge Devices—from smart cameras to dedicated AI box processors—bringing server-class intelligence to the edge. Job Description We are seeking a Principal Architect to define and own the architecture of our Unified Edge AI Engine. In this role, you will design the software backbone that orchestrates the entire lifecycle of video analytics on embedded hardware. You will act as the bridge between Systems Engineering and AI Research. Your mission is to build a modular, graph-based execution engine that balances massive data throughput with limited compute resources, enabling advanced AI models (optimized via quantization/pruning) to run in real-time across diverse hardware platforms. Scope of Responsibilities/Expectations: Pipeline Engine Architecture: Architect a modular, high-throughput Video & AI Pipeline Engine. Design the framework for dynamic graph construction (DAG) where AI models, logic nodes, and image processing blocks can be assembled and executed efficiently. Heterogeneous Resource Orchestration: Design the scheduling logic to balance workloads across CPU, GPU, DSP, and NPU. manage critical system bottlenecks such as PCIe Bandwidth, Memory Bandwidth, and Thermal constraints to prevent system stalls. AI Optimization Strategy: Define the architectural support for Model Quantization (INT8/FP16) and Network Pruning. Ensure the engine can natively handle optimized model formats, managing the trade-off between inference speed, memory footprint, and accuracy. Memory & Data Flow Design: Architect zero-copy data transport mechanisms (DMA, Shared Memory, Ring Buffers) to pass high-resolution video frames and tensor data between pipeline stages without CPU intervention. Scalability & Abstraction: Create a hardware-agnostic Abstraction Layer (HAL) that allows the engine to scale from low-power cameras to high-performance AI processors with minimal code changes. Basic Requirements System Architecture: Mastery of Modern C++ (14/17/20) and architectural patterns for high-concurrency, real-time systems. Deep understanding of Producer-Consumer models, Lock-free queues, and multi-threaded synchronization. AI Model Optimization: Strong knowledge of techniques to reduce model complexity: Quantization (PTQ/QAT), Weight Pruning, and Knowledge Distillation. Experience integrating these optimized models into C++ runtimes (e.g., TensorRT, SNPE/QNN, OpenVINO). Hardware Intimacy: Deep understanding of SoC architectures (Qualcomm, Ambarella, NVIDIA). Ability to analyze how Cache Coherency, Bus Arbitration, and Memory Controllers impact AI performance. Profiling & Analysis: Expert ability to use system profilers (e.g., Perf, eBPF, Nsight Systems) to visualize the "Critical Path" of the pipeline and optimize instruction-level performance. Pipeline Frameworks: Experience designing or heavily customizing media pipelines (similar to GStreamer, MediaPipe, or DeepStream). Basic Qualifications Bachelor’s Degree or higher in Embedded AI, Computer Science, Computer Engineering, or related technical fields. 10+ years of industry experience in Embedded Software Architecture or High-Performance Computing. Proven track record of designing complex software engines for Video Processing, Computer Vision, or Autonomous Systems. Experience acting as a System Architect, making critical decisions on resource allocation, memory management, and hardware selection. ... (truncated, view full listing at source)
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